PPC440           2966 arch/powerpc/xmon/ppc-opc.c #define PPC464	PPC440
PPC440           3523 arch/powerpc/xmon/ppc-opc.c {"udi0fcm.",	APU(4, 515,0),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC440           3524 arch/powerpc/xmon/ppc-opc.c {"udi0fcm",	APU(4, 515,1),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC440           3553 arch/powerpc/xmon/ppc-opc.c {"udi1fcm.",	APU(4, 547,0),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC440           3554 arch/powerpc/xmon/ppc-opc.c {"udi1fcm",	APU(4, 547,1),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC440           3593 arch/powerpc/xmon/ppc-opc.c {"udi2fcm.",	APU(4, 579,0),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC440           3594 arch/powerpc/xmon/ppc-opc.c {"udi2fcm",	APU(4, 579,1),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC440           3609 arch/powerpc/xmon/ppc-opc.c {"udi3fcm.",	APU(4, 611,0),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC440           3611 arch/powerpc/xmon/ppc-opc.c {"udi3fcm",	APU(4, 611,1),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC440           3635 arch/powerpc/xmon/ppc-opc.c {"udi4fcm.",	APU(4, 643,0),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC440           3636 arch/powerpc/xmon/ppc-opc.c {"udi4fcm",	APU(4, 643,1),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC440           3662 arch/powerpc/xmon/ppc-opc.c {"udi5fcm.",	APU(4, 675,0),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC440           3663 arch/powerpc/xmon/ppc-opc.c {"udi5fcm",	APU(4, 675,1),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC440           3694 arch/powerpc/xmon/ppc-opc.c {"udi6fcm.",	APU(4, 707,0),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC440           3695 arch/powerpc/xmon/ppc-opc.c {"udi6fcm",	APU(4, 707,1),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC440           3717 arch/powerpc/xmon/ppc-opc.c {"udi7fcm.",	APU(4, 739,0),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC440           3718 arch/powerpc/xmon/ppc-opc.c {"udi7fcm",	APU(4, 739,1),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC440           3751 arch/powerpc/xmon/ppc-opc.c {"udi8fcm.",	APU(4, 771,0),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
PPC440           3752 arch/powerpc/xmon/ppc-opc.c {"udi8fcm",	APU(4, 771,1),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
PPC440           3759 arch/powerpc/xmon/ppc-opc.c {"udi9fcm.",	APU(4, 804,0),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
PPC440           3760 arch/powerpc/xmon/ppc-opc.c {"udi9fcm",	APU(4, 804,1),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
PPC440           3767 arch/powerpc/xmon/ppc-opc.c {"udi10fcm.",	APU(4, 835,0),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
PPC440           3768 arch/powerpc/xmon/ppc-opc.c {"udi10fcm",	APU(4, 835,1),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
PPC440           3775 arch/powerpc/xmon/ppc-opc.c {"udi11fcm.",	APU(4, 867,0),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
PPC440           3777 arch/powerpc/xmon/ppc-opc.c {"udi11fcm",	APU(4, 867,1),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
PPC440           3784 arch/powerpc/xmon/ppc-opc.c {"udi12fcm.",	APU(4, 899,0),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
PPC440           3785 arch/powerpc/xmon/ppc-opc.c {"udi12fcm",	APU(4, 899,1),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
PPC440           3796 arch/powerpc/xmon/ppc-opc.c {"udi13fcm.",	APU(4, 931,0),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
PPC440           3797 arch/powerpc/xmon/ppc-opc.c {"udi13fcm",	APU(4, 931,1),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
PPC440           3806 arch/powerpc/xmon/ppc-opc.c {"udi14fcm.",	APU(4, 963,0),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
PPC440           3807 arch/powerpc/xmon/ppc-opc.c {"udi14fcm",	APU(4, 963,1),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
PPC440           3816 arch/powerpc/xmon/ppc-opc.c {"udi15fcm.",	APU(4, 995,0),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
PPC440           3818 arch/powerpc/xmon/ppc-opc.c {"udi15fcm",	APU(4, 995,1),	APU_MASK,    PPC440,	PPC476,		{URT, URA, URB}},
PPC440           4842 arch/powerpc/xmon/ppc-opc.c {"dlmzb",	XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, 0,		{RA, RS, RB}},
PPC440           4843 arch/powerpc/xmon/ppc-opc.c {"dlmzb.",	XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, 0,		{RA, RS, RB}},
PPC440           5539 arch/powerpc/xmon/ppc-opc.c {"dccci",	X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0,	{RAOPT, RBOPT}},
PPC440           5726 arch/powerpc/xmon/ppc-opc.c {"dcread",	X(31,486),	X_MASK,	 PPC403|PPC440, PPCA2|PPC476,	{RT, RA0, RB}},
PPC440           6213 arch/powerpc/xmon/ppc-opc.c {"iccci",	X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0,	 {RAOPT, RBOPT}},
PPC440           6245 arch/powerpc/xmon/ppc-opc.c {"icread",	X(31,998),     XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0,	{RA0, RB}},