PPC405           3293 arch/powerpc/xmon/ppc-opc.c {"get",		APU(4, 268,0),	APU_RA_MASK, PPC405,	0,		{RT, FSL}},
PPC405           3316 arch/powerpc/xmon/ppc-opc.c {"cget",	APU(4, 284,0),	APU_RA_MASK, PPC405,	0,		{RT, FSL}},
PPC405           3327 arch/powerpc/xmon/ppc-opc.c {"nget",	APU(4, 300,0),	APU_RA_MASK, PPC405,	0,		{RT, FSL}},
PPC405           3329 arch/powerpc/xmon/ppc-opc.c {"ncget",	APU(4, 316,0),	APU_RA_MASK, PPC405,	0,		{RT, FSL}},
PPC405           3358 arch/powerpc/xmon/ppc-opc.c {"put",		APU(4, 332,0),	APU_RT_MASK, PPC405,	0,		{RA, FSL}},
PPC405           3363 arch/powerpc/xmon/ppc-opc.c {"cput",	APU(4, 348,0),	APU_RT_MASK, PPC405,	0,		{RA, FSL}},
PPC405           3391 arch/powerpc/xmon/ppc-opc.c {"nput",	APU(4, 364,0),	APU_RT_MASK, PPC405,	0,		{RA, FSL}},
PPC405           3420 arch/powerpc/xmon/ppc-opc.c {"ncput",	APU(4, 380,0),	APU_RT_MASK, PPC405,	0,		{RA, FSL}},
PPC405           3523 arch/powerpc/xmon/ppc-opc.c {"udi0fcm.",	APU(4, 515,0),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC405           3524 arch/powerpc/xmon/ppc-opc.c {"udi0fcm",	APU(4, 515,1),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC405           3553 arch/powerpc/xmon/ppc-opc.c {"udi1fcm.",	APU(4, 547,0),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC405           3554 arch/powerpc/xmon/ppc-opc.c {"udi1fcm",	APU(4, 547,1),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC405           3593 arch/powerpc/xmon/ppc-opc.c {"udi2fcm.",	APU(4, 579,0),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC405           3594 arch/powerpc/xmon/ppc-opc.c {"udi2fcm",	APU(4, 579,1),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC405           3609 arch/powerpc/xmon/ppc-opc.c {"udi3fcm.",	APU(4, 611,0),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC405           3611 arch/powerpc/xmon/ppc-opc.c {"udi3fcm",	APU(4, 611,1),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC405           3635 arch/powerpc/xmon/ppc-opc.c {"udi4fcm.",	APU(4, 643,0),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC405           3636 arch/powerpc/xmon/ppc-opc.c {"udi4fcm",	APU(4, 643,1),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC405           3662 arch/powerpc/xmon/ppc-opc.c {"udi5fcm.",	APU(4, 675,0),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC405           3663 arch/powerpc/xmon/ppc-opc.c {"udi5fcm",	APU(4, 675,1),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC405           3694 arch/powerpc/xmon/ppc-opc.c {"udi6fcm.",	APU(4, 707,0),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC405           3695 arch/powerpc/xmon/ppc-opc.c {"udi6fcm",	APU(4, 707,1),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC405           3717 arch/powerpc/xmon/ppc-opc.c {"udi7fcm.",	APU(4, 739,0),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC405           3718 arch/powerpc/xmon/ppc-opc.c {"udi7fcm",	APU(4, 739,1),	APU_MASK, PPC405|PPC440, PPC476,	{URT, URA, URB}},
PPC405           4697 arch/powerpc/xmon/ppc-opc.c {"lbfcmx",	APU(31,7,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
PPC405           4771 arch/powerpc/xmon/ppc-opc.c {"lhfcmx",	APU(31,39,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
PPC405           4835 arch/powerpc/xmon/ppc-opc.c {"lwfcmx",	APU(31,71,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
PPC405           4861 arch/powerpc/xmon/ppc-opc.c {"lqfcmx",	APU(31,103,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
PPC405           4899 arch/powerpc/xmon/ppc-opc.c {"stbfcmx",	APU(31,135,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
PPC405           4951 arch/powerpc/xmon/ppc-opc.c {"sthfcmx",	APU(31,167,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
PPC405           4983 arch/powerpc/xmon/ppc-opc.c {"stwfcmx",	APU(31,199,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
PPC405           5023 arch/powerpc/xmon/ppc-opc.c {"stqfcmx",	APU(31,231,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
PPC405           5075 arch/powerpc/xmon/ppc-opc.c {"ldfcmx",	APU(31,263,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
PPC405           5240 arch/powerpc/xmon/ppc-opc.c {"mfsprg4",	XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0,		{RT}},
PPC405           5241 arch/powerpc/xmon/ppc-opc.c {"mfsprg5",	XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0,		{RT}},
PPC405           5242 arch/powerpc/xmon/ppc-opc.c {"mfsprg6",	XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0,		{RT}},
PPC405           5243 arch/powerpc/xmon/ppc-opc.c {"mfsprg7",	XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, 0,		{RT}},
PPC405           5350 arch/powerpc/xmon/ppc-opc.c {"mfccr0",	XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, 0,		{RT}},
PPC405           5351 arch/powerpc/xmon/ppc-opc.c {"mfiac3",	XSPR(31,339,948), XSPR_MASK, PPC405,	0,		{RT}},
PPC405           5352 arch/powerpc/xmon/ppc-opc.c {"mfiac4",	XSPR(31,339,949), XSPR_MASK, PPC405,	0,		{RT}},
PPC405           5353 arch/powerpc/xmon/ppc-opc.c {"mfdvc1",	XSPR(31,339,950), XSPR_MASK, PPC405,	0,		{RT}},
PPC405           5354 arch/powerpc/xmon/ppc-opc.c {"mfdvc2",	XSPR(31,339,951), XSPR_MASK, PPC405,	0,		{RT}},
PPC405           5361 arch/powerpc/xmon/ppc-opc.c {"mfsler",	XSPR(31,339,955), XSPR_MASK, PPC405,	0,		{RT}},
PPC405           5363 arch/powerpc/xmon/ppc-opc.c {"mfsu0r",	XSPR(31,339,956), XSPR_MASK, PPC405,	0,		{RT}},
PPC405           5364 arch/powerpc/xmon/ppc-opc.c {"mfdbcr1",	XSPR(31,339,957), XSPR_MASK, PPC405,	0,		{RT}},
PPC405           5380 arch/powerpc/xmon/ppc-opc.c {"mfdbcr0",	XSPR(31,339,1010), XSPR_MASK, PPC405,	0,		{RT}},
PPC405           5435 arch/powerpc/xmon/ppc-opc.c {"stdfcmx",	APU(31,391,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
PPC405           5600 arch/powerpc/xmon/ppc-opc.c {"mtsprg4",	XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, 0,		{RS}},
PPC405           5601 arch/powerpc/xmon/ppc-opc.c {"mtsprg5",	XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, 0,		{RS}},
PPC405           5602 arch/powerpc/xmon/ppc-opc.c {"mtsprg6",	XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, 0,		{RS}},
PPC405           5603 arch/powerpc/xmon/ppc-opc.c {"mtsprg7",	XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, 0,		{RS}},
PPC405           5670 arch/powerpc/xmon/ppc-opc.c {"mtccr0",	XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, 0,		{RS}},
PPC405           5671 arch/powerpc/xmon/ppc-opc.c {"mtiac3",	XSPR(31,467,948), XSPR_MASK, PPC405,	0,		{RS}},
PPC405           5672 arch/powerpc/xmon/ppc-opc.c {"mtiac4",	XSPR(31,467,949), XSPR_MASK, PPC405,	0,		{RS}},
PPC405           5673 arch/powerpc/xmon/ppc-opc.c {"mtdvc1",	XSPR(31,467,950), XSPR_MASK, PPC405,	0,		{RS}},
PPC405           5674 arch/powerpc/xmon/ppc-opc.c {"mtdvc2",	XSPR(31,467,951), XSPR_MASK, PPC405,	0,		{RS}},
PPC405           5681 arch/powerpc/xmon/ppc-opc.c {"mtsler",	XSPR(31,467,955), XSPR_MASK, PPC405,	0,		{RS}},
PPC405           5683 arch/powerpc/xmon/ppc-opc.c {"mtsu0r",	XSPR(31,467,956), XSPR_MASK, PPC405,	0,		{RS}},
PPC405           5684 arch/powerpc/xmon/ppc-opc.c {"mtdbcr1",	XSPR(31,467,957), XSPR_MASK, PPC405,	0,		{RS}},
PPC405           5701 arch/powerpc/xmon/ppc-opc.c {"mtdbcr0",	XSPR(31,467,1010), XSPR_MASK, PPC405,	0,		{RS}},
PPC405           5760 arch/powerpc/xmon/ppc-opc.c {"lbfcmux",	APU(31,519,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
PPC405           5813 arch/powerpc/xmon/ppc-opc.c {"lhfcmux",	APU(31,551,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
PPC405           5836 arch/powerpc/xmon/ppc-opc.c {"lwfcmux",	APU(31,583,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
PPC405           5866 arch/powerpc/xmon/ppc-opc.c {"lqfcmux",	APU(31,615,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
PPC405           5884 arch/powerpc/xmon/ppc-opc.c {"stbfcmux",	APU(31,647,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
PPC405           5924 arch/powerpc/xmon/ppc-opc.c {"sthfcmux",	APU(31,679,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
PPC405           5943 arch/powerpc/xmon/ppc-opc.c {"stwfcmux",	APU(31,711,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
PPC405           5981 arch/powerpc/xmon/ppc-opc.c {"stqfcmux",	APU(31,743,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
PPC405           6007 arch/powerpc/xmon/ppc-opc.c {"dcba",	X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
PPC405           6021 arch/powerpc/xmon/ppc-opc.c {"ldfcmux",	APU(31,775,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
PPC405           6138 arch/powerpc/xmon/ppc-opc.c {"stdfcmux",	APU(31,903,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},