POWER4 3037 arch/powerpc/xmon/ppc-opc.c {"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476|PPCVLE, {0}}, POWER4 5053 arch/powerpc/xmon/ppc-opc.c {"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}}, POWER4 5055 arch/powerpc/xmon/ppc-opc.c {"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}}, POWER4 5094 arch/powerpc/xmon/ppc-opc.c {"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, LOPT}}, POWER4 5104 arch/powerpc/xmon/ppc-opc.c {"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}}, POWER4 5106 arch/powerpc/xmon/ppc-opc.c {"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}}, POWER4 5220 arch/powerpc/xmon/ppc-opc.c {"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, 0, {RT}}, POWER4 5244 arch/powerpc/xmon/ppc-opc.c {"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, 0, {RT}}, POWER4 5245 arch/powerpc/xmon/ppc-opc.c {"mftb", X(31,339), X_MASK, POWER4|BOOKE, 0, {RT, TBR}}, POWER4 5246 arch/powerpc/xmon/ppc-opc.c {"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, 0, {RT}}, POWER4 5417 arch/powerpc/xmon/ppc-opc.c {"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}}, POWER4 5418 arch/powerpc/xmon/ppc-opc.c {"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}}, POWER4 5419 arch/powerpc/xmon/ppc-opc.c {"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4, {RT}}, POWER4 5584 arch/powerpc/xmon/ppc-opc.c {"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, 0, {RS}}, POWER4 5845 arch/powerpc/xmon/ppc-opc.c {"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}}, POWER4 6269 arch/powerpc/xmon/ppc-opc.c {"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}}, POWER4 6338 arch/powerpc/xmon/ppc-opc.c {"lq", OP(56), OP_MASK, POWER4, PPC476|PPCVLE, {RTQ, DQ, RAQ}}, POWER4 6675 arch/powerpc/xmon/ppc-opc.c {"stq", DSO(62,2), DS_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}},