PORT_REG         4963 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c 		int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
PORT_REG         4979 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c 	t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
PORT_REG         6364 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c 	(is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
PORT_REG         6461 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c 	PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
PORT_REG         9208 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c 				       PORT_REG(port, XGMAC_PORT_CFG_A) :
PORT_REG         1828 drivers/pinctrl/pinctrl-pic32.c 	return !!(readl(bank->reg_base + PORT_REG) & BIT(offset));
PORT_REG         1838 drivers/pinctrl/pinctrl-pic32.c 		writel(mask, bank->reg_base + PIC32_SET(PORT_REG));
PORT_REG         1840 drivers/pinctrl/pinctrl-pic32.c 		writel(mask, bank->reg_base + PIC32_CLR(PORT_REG));