PLL_RESET_N 333 drivers/clk/qcom/clk-alpha-pll.c mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; PLL_RESET_N 363 drivers/clk/qcom/clk-alpha-pll.c PLL_RESET_N, PLL_RESET_N); PLL_RESET_N 402 drivers/clk/qcom/clk-alpha-pll.c mask = PLL_RESET_N | PLL_BYPASSNL; PLL_RESET_N 845 drivers/clk/qcom/clk-alpha-pll.c regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); PLL_RESET_N 1036 drivers/clk/qcom/clk-alpha-pll.c regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); PLL_RESET_N 1075 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N 1076 drivers/clk/qcom/clk-alpha-pll.c PLL_RESET_N); PLL_RESET_N 72 drivers/clk/qcom/clk-hfpll.c regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N); PLL_RESET_N 98 drivers/clk/qcom/clk-hfpll.c if (!(mode & (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL))) PLL_RESET_N 115 drivers/clk/qcom/clk-hfpll.c PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL, 0); PLL_RESET_N 207 drivers/clk/qcom/clk-hfpll.c if (mode != (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL)) { PLL_RESET_N 232 drivers/clk/qcom/clk-hfpll.c return mode == (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL); PLL_RESET_N 30 drivers/clk/qcom/clk-pll.c mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; PLL_RESET_N 52 drivers/clk/qcom/clk-pll.c ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, PLL_RESET_N 53 drivers/clk/qcom/clk-pll.c PLL_RESET_N); PLL_RESET_N 75 drivers/clk/qcom/clk-pll.c mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; PLL_RESET_N 147 drivers/clk/qcom/clk-pll.c u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N; PLL_RESET_N 286 drivers/clk/qcom/clk-pll.c ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, PLL_RESET_N 287 drivers/clk/qcom/clk-pll.c PLL_RESET_N); PLL_RESET_N 307 drivers/clk/qcom/clk-pll.c u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N;