PLL_REF_DIV      1344 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 	calc_pll_cs_init_data.max_pll_ref_divider =	clk_src->cs_mask->PLL_REF_DIV;
PLL_REF_DIV      1363 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 	calc_pll_cs_init_data_hdmi.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV;
PLL_REF_DIV        52 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 	CS_SF(PLL_REF_DIV, PLL_REF_DIV, mask_sh)
PLL_REF_DIV       137 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 	type PLL_REF_DIV; \
PLL_REF_DIV      2435 drivers/video/fbdev/aty/atyfb_base.c 		u8 pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
PLL_REF_DIV      3065 drivers/video/fbdev/aty/atyfb_base.c 		M = pll_regs[PLL_REF_DIV];
PLL_REF_DIV       388 drivers/video/fbdev/aty/mach64_ct.c 	pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
PLL_REF_DIV       514 drivers/video/fbdev/aty/mach64_ct.c 		pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
PLL_REF_DIV       627 drivers/video/fbdev/aty/mach64_ct.c 	aty_st_pll_ct(PLL_REF_DIV, pll->ct.pll_ref_div, par);