PLL_DIV           192 arch/mips/ar7/clock.c 	if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) {
PLL_DIV            71 drivers/clk/at91/clk-pll.c 	div = PLL_DIV(pllr);
PLL_DIV           304 drivers/clk/at91/clk-pll.c 	pll->div = PLL_DIV(pllr);
PLL_DIV           470 drivers/mfd/db8500-prcmu.c 	CLK_MGT_ENTRY(SGACLK, PLL_DIV, false),
PLL_DIV           475 drivers/mfd/db8500-prcmu.c 	CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true),
PLL_DIV           477 drivers/mfd/db8500-prcmu.c 	CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true),
PLL_DIV           478 drivers/mfd/db8500-prcmu.c 	CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true),
PLL_DIV           479 drivers/mfd/db8500-prcmu.c 	CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true),
PLL_DIV           480 drivers/mfd/db8500-prcmu.c 	CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true),
PLL_DIV           481 drivers/mfd/db8500-prcmu.c 	CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
PLL_DIV           482 drivers/mfd/db8500-prcmu.c 	CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
PLL_DIV           484 drivers/mfd/db8500-prcmu.c 	CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
PLL_DIV           485 drivers/mfd/db8500-prcmu.c 	CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
PLL_DIV           486 drivers/mfd/db8500-prcmu.c 	CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
PLL_DIV           488 drivers/mfd/db8500-prcmu.c 	CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true),
PLL_DIV           489 drivers/mfd/db8500-prcmu.c 	CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true),
PLL_DIV           490 drivers/mfd/db8500-prcmu.c 	CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true),
PLL_DIV           493 drivers/mfd/db8500-prcmu.c 	CLK_MGT_ENTRY(DMACLK, PLL_DIV, true),
PLL_DIV           494 drivers/mfd/db8500-prcmu.c 	CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true),
PLL_DIV          1494 drivers/mfd/db8500-prcmu.c 	if ((branch == PLL_FIX) || ((branch == PLL_DIV) &&
PLL_DIV          1570 drivers/mfd/db8500-prcmu.c 		rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV);