PLL_CNTL          486 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 	REG_GET(PLL_CNTL, PLL_REF_DIV_SRC, &field);
PLL_CNTL           35 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRI(PLL_CNTL, BPHYC_PLL, id)
PLL_CNTL           39 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRI(PLL_CNTL, DCCG_PLL, id)
PLL_CNTL           49 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 	CS_SF(PLL_CNTL, PLL_REF_DIV_SRC, mask_sh),\
PLL_CNTL          153 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 	uint32_t PLL_CNTL;
PLL_CNTL          819 drivers/video/fbdev/i740fb.c 	i740outreg(par, XRX, PLL_CNTL, par->pll_cntl);