PIPE_FIFO_UNDERRUN_STATUS   98 drivers/gpu/drm/i915/display/intel_fifo_underrun.c 	if ((I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)
PIPE_FIFO_UNDERRUN_STATUS  102 drivers/gpu/drm/i915/display/intel_fifo_underrun.c 	I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
PIPE_FIFO_UNDERRUN_STATUS  121 drivers/gpu/drm/i915/display/intel_fifo_underrun.c 		I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
PIPE_FIFO_UNDERRUN_STATUS  124 drivers/gpu/drm/i915/display/intel_fifo_underrun.c 		if (old && I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS)
PIPE_FIFO_UNDERRUN_STATUS  617 drivers/gpu/drm/i915/i915_irq.c 	enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
PIPE_FIFO_UNDERRUN_STATUS 1710 drivers/gpu/drm/i915/i915_irq.c 			   PIPE_FIFO_UNDERRUN_STATUS);
PIPE_FIFO_UNDERRUN_STATUS 1741 drivers/gpu/drm/i915/i915_irq.c 		status_mask = PIPE_FIFO_UNDERRUN_STATUS;
PIPE_FIFO_UNDERRUN_STATUS 1793 drivers/gpu/drm/i915/i915_irq.c 		if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
PIPE_FIFO_UNDERRUN_STATUS 1814 drivers/gpu/drm/i915/i915_irq.c 		if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
PIPE_FIFO_UNDERRUN_STATUS 1838 drivers/gpu/drm/i915/i915_irq.c 		if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
PIPE_FIFO_UNDERRUN_STATUS 1861 drivers/gpu/drm/i915/i915_irq.c 		if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)