PIPE_DATA_M1 5229 drivers/gpu/drm/i915/display/intel_display.c I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); PIPE_DATA_M1 7655 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); PIPE_DATA_M1 9716 drivers/gpu/drm/i915/display/intel_display.c m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) PIPE_DATA_M1 9719 drivers/gpu/drm/i915/display/intel_display.c m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) PIPE_DATA_M1 231 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT; PIPE_DATA_M1 232 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e; PIPE_DATA_M1 2126 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL); PIPE_DATA_M1 2135 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL); PIPE_DATA_M1 2144 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL); PIPE_DATA_M1 2153 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);