PIPE_B 742 drivers/gpu/drm/i915/display/icl_dsi.c case PIPE_B: PIPE_B 1323 drivers/gpu/drm/i915/display/icl_dsi.c *pipe = PIPE_B; PIPE_B 1587 drivers/gpu/drm/i915/display/icl_dsi.c encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); PIPE_B 1815 drivers/gpu/drm/i915/display/intel_ddi.c case PIPE_B: PIPE_B 2004 drivers/gpu/drm/i915/display/intel_ddi.c *pipe_mask = BIT(PIPE_B); PIPE_B 1327 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, PIPE_B 1345 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, PIPE_B 1460 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); PIPE_B 1468 drivers/gpu/drm/i915/display/intel_display.c WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); PIPE_B 5139 drivers/gpu/drm/i915/display/intel_display.c WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); PIPE_B 5159 drivers/gpu/drm/i915/display/intel_display.c case PIPE_B: PIPE_B 6869 drivers/gpu/drm/i915/display/intel_display.c if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { PIPE_B 7214 drivers/gpu/drm/i915/display/intel_display.c case PIPE_B: PIPE_B 7237 drivers/gpu/drm/i915/display/intel_display.c other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B); PIPE_B 7767 drivers/gpu/drm/i915/display/intel_display.c if (pipe == PIPE_B) PIPE_B 8177 drivers/gpu/drm/i915/display/intel_display.c (pipe == PIPE_B || pipe == PIPE_C)) PIPE_B 8550 drivers/gpu/drm/i915/display/intel_display.c if (crtc->pipe != PIPE_B) PIPE_B 8630 drivers/gpu/drm/i915/display/intel_display.c if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B && PIPE_B 10262 drivers/gpu/drm/i915/display/intel_display.c trans_pipe = PIPE_B; PIPE_B 14922 drivers/gpu/drm/i915/display/intel_display.c if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { PIPE_B 16366 drivers/gpu/drm/i915/display/intel_display.c WARN_ON(I915_READ(CURCNTR(PIPE_B)) & MCURSOR_MODE); PIPE_B 101 drivers/gpu/drm/i915/display/intel_display.h TRANSCODER_B = PIPE_B, PIPE_B 1029 drivers/gpu/drm/i915/display/intel_display_power.c if ((I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0) PIPE_B 1030 drivers/gpu/drm/i915/display/intel_display_power.c i830_enable_pipe(dev_priv, PIPE_B); PIPE_B 1036 drivers/gpu/drm/i915/display/intel_display_power.c i830_disable_pipe(dev_priv, PIPE_B); PIPE_B 1044 drivers/gpu/drm/i915/display/intel_display_power.c I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; PIPE_B 1341 drivers/gpu/drm/i915/display/intel_display_power.c (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) PIPE_B 1465 drivers/gpu/drm/i915/display/intel_display_power.c assert_pll_disabled(dev_priv, PIPE_B); PIPE_B 2750 drivers/gpu/drm/i915/display/intel_display_power.c .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), PIPE_B 2951 drivers/gpu/drm/i915/display/intel_display_power.c .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), PIPE_B 3033 drivers/gpu/drm/i915/display/intel_display_power.c .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), PIPE_B 3093 drivers/gpu/drm/i915/display/intel_display_power.c .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), PIPE_B 3262 drivers/gpu/drm/i915/display/intel_display_power.c .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), PIPE_B 3401 drivers/gpu/drm/i915/display/intel_display_power.c .hsw.irq_pipe_mask = BIT(PIPE_B), PIPE_B 3634 drivers/gpu/drm/i915/display/intel_display_power.c .hsw.irq_pipe_mask = BIT(PIPE_B), PIPE_B 1332 drivers/gpu/drm/i915/display/intel_display_types.h case PIPE_B: PIPE_B 799 drivers/gpu/drm/i915/display/intel_dp.c unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); PIPE_B 928 drivers/gpu/drm/i915/display/intel_dp.c for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { PIPE_B 3494 drivers/gpu/drm/i915/display/intel_dp.c if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) PIPE_B 4097 drivers/gpu/drm/i915/display/intel_dp.c if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) { PIPE_B 7080 drivers/gpu/drm/i915/display/intel_dp.c if (pipe != PIPE_A && pipe != PIPE_B) PIPE_B 7083 drivers/gpu/drm/i915/display/intel_dp.c if (pipe != PIPE_A && pipe != PIPE_B) PIPE_B 797 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (ch == DPIO_CH0 && pipe == PIPE_B) PIPE_B 809 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (pipe != PIPE_B) { PIPE_B 830 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (pipe != PIPE_B) PIPE_B 839 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (pipe != PIPE_B) PIPE_B 852 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (pipe != PIPE_B) PIPE_B 962 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (pipe != PIPE_B) { PIPE_B 2011 drivers/gpu/drm/i915/display/intel_hdmi.c if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { PIPE_B 572 drivers/gpu/drm/i915/display/intel_panel.c if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) PIPE_B 1734 drivers/gpu/drm/i915/display/intel_panel.c if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) PIPE_B 182 drivers/gpu/drm/i915/display/intel_pipe_crc.c case PIPE_B: PIPE_B 246 drivers/gpu/drm/i915/display/intel_pipe_crc.c case PIPE_B: PIPE_B 1747 drivers/gpu/drm/i915/display/intel_sdvo.c if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { PIPE_B 966 drivers/gpu/drm/i915/display/intel_sprite.c if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) PIPE_B 2598 drivers/gpu/drm/i915/display/intel_sprite.c if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { PIPE_B 992 drivers/gpu/drm/i915/display/vlv_dsi.c enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; PIPE_B 1016 drivers/gpu/drm/i915/display/vlv_dsi.c *pipe = port == PORT_A ? PIPE_A : PIPE_B; PIPE_B 1873 drivers/gpu/drm/i915/display/vlv_dsi.c intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); PIPE_B 1877 drivers/gpu/drm/i915/display/vlv_dsi.c intel_encoder->crtc_mask = BIT(PIPE_B); PIPE_B 1217 drivers/gpu/drm/i915/gvt/cmd_parser.c [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE}, PIPE_B 1219 drivers/gpu/drm/i915/gvt/cmd_parser.c [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE}, PIPE_B 1275 drivers/gpu/drm/i915/gvt/cmd_parser.c info->pipe = PIPE_B; PIPE_B 1289 drivers/gpu/drm/i915/gvt/cmd_parser.c info->pipe = PIPE_B; PIPE_B 49 drivers/gpu/drm/i915/gvt/display.c pipe = PIPE_B; PIPE_B 435 drivers/gpu/drm/i915/gvt/display.c [PIPE_B] = PIPE_B_VBLANK, PIPE_B 1960 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPEDSL(PIPE_B), D_ALL); PIPE_B 1965 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); PIPE_B 1970 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPESTAT(PIPE_B), D_ALL); PIPE_B 1975 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL); PIPE_B 1980 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL); PIPE_B 1985 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(CURCNTR(PIPE_B), D_ALL); PIPE_B 1989 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(CURPOS(PIPE_B), D_ALL); PIPE_B 1993 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(CURBASE(PIPE_B), D_ALL); PIPE_B 1997 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL); PIPE_B 2020 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPCNTR(PIPE_B), D_ALL); PIPE_B 2021 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPADDR(PIPE_B), D_ALL); PIPE_B 2022 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPSTRIDE(PIPE_B), D_ALL); PIPE_B 2023 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPPOS(PIPE_B), D_ALL); PIPE_B 2024 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPSIZE(PIPE_B), D_ALL); PIPE_B 2025 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); PIPE_B 2026 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPOFFSET(PIPE_B), D_ALL); PIPE_B 2027 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL); PIPE_B 2028 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL, PIPE_B 2057 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRCTL(PIPE_B), D_ALL); PIPE_B 2058 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRLINOFF(PIPE_B), D_ALL); PIPE_B 2059 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRSTRIDE(PIPE_B), D_ALL); PIPE_B 2060 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRPOS(PIPE_B), D_ALL); PIPE_B 2061 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRSIZE(PIPE_B), D_ALL); PIPE_B 2062 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRKEYVAL(PIPE_B), D_ALL); PIPE_B 2063 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRKEYMSK(PIPE_B), D_ALL); PIPE_B 2064 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); PIPE_B 2065 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRKEYMAX(PIPE_B), D_ALL); PIPE_B 2066 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPROFFSET(PIPE_B), D_ALL); PIPE_B 2067 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRSCALE(PIPE_B), D_ALL); PIPE_B 2068 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL); PIPE_B 2069 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL, PIPE_B 2168 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PF_CTL(PIPE_B), D_ALL); PIPE_B 2169 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL); PIPE_B 2170 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PF_WIN_POS(PIPE_B), D_ALL); PIPE_B 2171 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PF_VSCALE(PIPE_B), D_ALL); PIPE_B 2172 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PF_HSCALE(PIPE_B), D_ALL); PIPE_B 2215 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); PIPE_B 2218 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); PIPE_B 2221 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); PIPE_B 2250 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL); PIPE_B 2257 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL); PIPE_B 2258 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL); PIPE_B 2259 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL); PIPE_B 2348 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL); PIPE_B 2349 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL); PIPE_B 2350 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL); PIPE_B 2351 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL); PIPE_B 2352 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL); PIPE_B 2353 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL); PIPE_B 2354 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL); PIPE_B 2355 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL); PIPE_B 2356 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL); PIPE_B 2357 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL); PIPE_B 2358 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL); PIPE_B 2359 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL); PIPE_B 2360 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL); PIPE_B 2380 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL); PIPE_B 2381 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL); PIPE_B 2382 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); PIPE_B 2401 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL); PIPE_B 2427 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GAMMA_MODE(PIPE_B), D_ALL); PIPE_B 2431 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_MULT(PIPE_B), D_ALL); PIPE_B 2707 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, PIPE_B 2709 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, PIPE_B 2711 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, PIPE_B 2713 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS); PIPE_B 2772 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS); PIPE_B 2795 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS); PIPE_B 2910 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); PIPE_B 2911 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); PIPE_B 2917 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); PIPE_B 2918 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); PIPE_B 2924 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); PIPE_B 2925 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); PIPE_B 2934 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); PIPE_B 2935 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); PIPE_B 2936 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); PIPE_B 2937 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); PIPE_B 2945 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL); PIPE_B 2952 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); PIPE_B 2953 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); PIPE_B 2954 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); PIPE_B 2961 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); PIPE_B 2968 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); PIPE_B 2969 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); PIPE_B 2970 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); PIPE_B 2977 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL); PIPE_B 2985 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); PIPE_B 2986 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); PIPE_B 2987 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); PIPE_B 2988 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); PIPE_B 3000 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); PIPE_B 3001 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); PIPE_B 3002 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); PIPE_B 3003 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); PIPE_B 3015 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); PIPE_B 3016 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); PIPE_B 3017 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); PIPE_B 3018 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); PIPE_B 3087 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS); PIPE_B 3090 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS); PIPE_B 3093 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS); PIPE_B 3333 drivers/gpu/drm/i915/gvt/handlers.c {D_ALL, LGC_PALETTE(PIPE_B, 0), 1024, NULL, NULL}, PIPE_B 450 drivers/gpu/drm/i915/gvt/interrupt.c DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_b, GEN8_DE_PIPE_ISR(PIPE_B)); PIPE_B 74 drivers/gpu/drm/i915/gvt/reg.h (((p) == PIPE_B) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50088)) : \ PIPE_B 83 drivers/gpu/drm/i915/gvt/reg.h (((reg) == 0x50088 || (reg) == 0x50098) ? (PIPE_B) : \ PIPE_B 699 drivers/gpu/drm/i915/i915_irq.c i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); PIPE_B 1747 drivers/gpu/drm/i915/i915_irq.c case PIPE_B: PIPE_B 2182 drivers/gpu/drm/i915/i915_irq.c intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); PIPE_B 3932 drivers/gpu/drm/i915/i915_irq.c i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); PIPE_B 4106 drivers/gpu/drm/i915/i915_irq.c i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); PIPE_B 4224 drivers/gpu/drm/i915/i915_irq.c i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); PIPE_B 104 drivers/gpu/drm/i915/i915_pci.c [PIPE_B] = CURSOR_B_OFFSET, \ PIPE_B 110 drivers/gpu/drm/i915/i915_pci.c [PIPE_B] = CURSOR_B_OFFSET, \ PIPE_B 117 drivers/gpu/drm/i915/i915_pci.c [PIPE_B] = IVB_CURSOR_B_OFFSET, \ PIPE_B 7962 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 7965 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 7968 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 7971 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 7990 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 7993 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 7996 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 7999 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 8015 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 8018 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 8021 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 8024 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 8040 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 8043 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 8046 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 8049 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 10510 drivers/gpu/drm/i915/i915_reg.h #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 10519 drivers/gpu/drm/i915/i915_reg.h #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11244 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11247 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11265 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11268 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11279 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11282 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11294 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11297 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11309 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11312 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11324 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11327 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11339 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11342 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11356 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11359 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11371 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11374 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11386 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11389 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11401 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11404 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11418 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11421 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11431 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11434 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11444 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11447 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11457 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11460 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11470 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11473 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11483 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11486 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11506 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11509 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11512 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11515 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11531 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11534 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11537 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 11540 drivers/gpu/drm/i915/i915_reg.h #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ PIPE_B 45 drivers/gpu/drm/i915/i915_trace.h __entry->frame[PIPE_B], __entry->scanline[PIPE_B], PIPE_B 72 drivers/gpu/drm/i915/i915_trace.h __entry->frame[PIPE_B], __entry->scanline[PIPE_B], PIPE_B 169 drivers/gpu/drm/i915/i915_trace.h __entry->frame[PIPE_B], __entry->scanline[PIPE_B], PIPE_B 870 drivers/gpu/drm/i915/intel_device_info.c runtime->num_scalers[PIPE_B] = 2; PIPE_B 893 drivers/gpu/drm/i915/intel_device_info.c runtime->num_sprites[PIPE_B] = 2; PIPE_B 938 drivers/gpu/drm/i915/intel_device_info.c enabled_mask &= ~BIT(PIPE_B); PIPE_B 509 drivers/gpu/drm/i915/intel_pm.c case PIPE_B: PIPE_B 959 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | PIPE_B 960 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | PIPE_B 966 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) | PIPE_B 1009 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | PIPE_B 1010 drivers/gpu/drm/i915/intel_pm.c FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | PIPE_B 1021 drivers/gpu/drm/i915/intel_pm.c FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) | PIPE_B 1022 drivers/gpu/drm/i915/intel_pm.c FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC)); PIPE_B 1034 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) | PIPE_B 1035 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) | PIPE_B 1036 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) | PIPE_B 1042 drivers/gpu/drm/i915/intel_pm.c FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) | PIPE_B 1043 drivers/gpu/drm/i915/intel_pm.c FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC)); PIPE_B 1046 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) | PIPE_B 1047 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) | PIPE_B 1048 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) | PIPE_B 2009 drivers/gpu/drm/i915/intel_pm.c case PIPE_B: PIPE_B 3564 drivers/gpu/drm/i915/intel_pm.c if (dirty & WM_DIRTY_PIPE(PIPE_B)) PIPE_B 3571 drivers/gpu/drm/i915/intel_pm.c if (dirty & WM_DIRTY_LINETIME(PIPE_B)) PIPE_B 3572 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); PIPE_B 5838 drivers/gpu/drm/i915/intel_pm.c [PIPE_B] = WM0_PIPEB_ILK, PIPE_B 5891 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB); PIPE_B 5892 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB); PIPE_B 5899 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB); PIPE_B 5931 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB); PIPE_B 5932 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB); PIPE_B 5945 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED); PIPE_B 5946 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC); PIPE_B 5961 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8; PIPE_B 5962 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8; PIPE_B 5963 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8; PIPE_B 5969 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED); PIPE_B 5970 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC); PIPE_B 5974 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8; PIPE_B 5975 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8; PIPE_B 5976 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8; PIPE_B 1059 drivers/video/fbdev/intelfb/intelfbhw.c if (pipe == PIPE_B) { PIPE_B 1302 drivers/video/fbdev/intelfb/intelfbhw.c if (dinfo->pipe == PIPE_B) {