PIPE_A 739 drivers/gpu/drm/i915/display/icl_dsi.c case PIPE_A: PIPE_A 1320 drivers/gpu/drm/i915/display/icl_dsi.c *pipe = PIPE_A; PIPE_A 1587 drivers/gpu/drm/i915/display/icl_dsi.c encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); PIPE_A 235 drivers/gpu/drm/i915/display/intel_crt.c intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); PIPE_A 255 drivers/gpu/drm/i915/display/intel_crt.c intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); PIPE_A 266 drivers/gpu/drm/i915/display/intel_crt.c intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); PIPE_A 301 drivers/gpu/drm/i915/display/intel_crt.c intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); PIPE_A 1069 drivers/gpu/drm/i915/display/intel_crt.c dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; PIPE_A 1085 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | PIPE_A 1093 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); PIPE_A 1094 drivers/gpu/drm/i915/display/intel_ddi.c POSTING_READ(FDI_RX_CTL(PIPE_A)); PIPE_A 1099 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); PIPE_A 1129 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); PIPE_A 1133 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); PIPE_A 1134 drivers/gpu/drm/i915/display/intel_ddi.c POSTING_READ(FDI_RX_CTL(PIPE_A)); PIPE_A 1140 drivers/gpu/drm/i915/display/intel_ddi.c temp = I915_READ(FDI_RX_MISC(PIPE_A)); PIPE_A 1142 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(FDI_RX_MISC(PIPE_A), temp); PIPE_A 1143 drivers/gpu/drm/i915/display/intel_ddi.c POSTING_READ(FDI_RX_MISC(PIPE_A)); PIPE_A 1164 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); PIPE_A 1165 drivers/gpu/drm/i915/display/intel_ddi.c POSTING_READ(FDI_RX_CTL(PIPE_A)); PIPE_A 1182 drivers/gpu/drm/i915/display/intel_ddi.c temp = I915_READ(FDI_RX_MISC(PIPE_A)); PIPE_A 1185 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(FDI_RX_MISC(PIPE_A), temp); PIPE_A 1186 drivers/gpu/drm/i915/display/intel_ddi.c POSTING_READ(FDI_RX_MISC(PIPE_A)); PIPE_A 1805 drivers/gpu/drm/i915/display/intel_ddi.c case PIPE_A: PIPE_A 2001 drivers/gpu/drm/i915/display/intel_ddi.c *pipe_mask = BIT(PIPE_A); PIPE_A 3448 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(FDI_RX_CTL(PIPE_A)); PIPE_A 3450 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(FDI_RX_CTL(PIPE_A), val); PIPE_A 3455 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(FDI_RX_MISC(PIPE_A)); PIPE_A 3458 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(FDI_RX_MISC(PIPE_A), val); PIPE_A 3460 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(FDI_RX_CTL(PIPE_A)); PIPE_A 3462 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(FDI_RX_CTL(PIPE_A), val); PIPE_A 3464 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(FDI_RX_CTL(PIPE_A)); PIPE_A 3466 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(FDI_RX_CTL(PIPE_A), val); PIPE_A 3993 drivers/gpu/drm/i915/display/intel_ddi.c if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && PIPE_A 1452 drivers/gpu/drm/i915/display/intel_display.c if (pipe != PIPE_A) { PIPE_A 1555 drivers/gpu/drm/i915/display/intel_display.c if (pipe != PIPE_A) PIPE_A 1572 drivers/gpu/drm/i915/display/intel_display.c if (pipe != PIPE_A) PIPE_A 1684 drivers/gpu/drm/i915/display/intel_display.c assert_fdi_rx_enabled(dev_priv, PIPE_A); PIPE_A 1687 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(TRANS_CHICKEN2(PIPE_A)); PIPE_A 1689 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); PIPE_A 1749 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(TRANS_CHICKEN2(PIPE_A)); PIPE_A 1751 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); PIPE_A 1759 drivers/gpu/drm/i915/display/intel_display.c return PIPE_A; PIPE_A 2506 drivers/gpu/drm/i915/display/intel_display.c crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A); PIPE_A 5157 drivers/gpu/drm/i915/display/intel_display.c case PIPE_A: PIPE_A 5303 drivers/gpu/drm/i915/display/intel_display.c assert_pch_transcoder_disabled(dev_priv, PIPE_A); PIPE_A 5308 drivers/gpu/drm/i915/display/intel_display.c ironlake_pch_transcoder_set_timings(crtc_state, PIPE_A); PIPE_A 6403 drivers/gpu/drm/i915/display/intel_display.c return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; PIPE_A 7212 drivers/gpu/drm/i915/display/intel_display.c case PIPE_A: PIPE_A 7368 drivers/gpu/drm/i915/display/intel_display.c (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); PIPE_A 7709 drivers/gpu/drm/i915/display/intel_display.c if (crtc->pipe != PIPE_A) PIPE_A 7726 drivers/gpu/drm/i915/display/intel_display.c if (crtc->pipe != PIPE_A) PIPE_A 7810 drivers/gpu/drm/i915/display/intel_display.c if (pipe == PIPE_A) PIPE_A 7818 drivers/gpu/drm/i915/display/intel_display.c if (pipe == PIPE_A) PIPE_A 8830 drivers/gpu/drm/i915/display/intel_display.c if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) PIPE_A 10259 drivers/gpu/drm/i915/display/intel_display.c trans_pipe = PIPE_A; PIPE_A 10392 drivers/gpu/drm/i915/display/intel_display.c tmp = I915_READ(FDI_RX_CTL(PIPE_A)); PIPE_A 10731 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE_FW(CURCNTR(PIPE_A), 0); PIPE_A 10732 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE_FW(CURBASE(PIPE_A), base); PIPE_A 10734 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE_FW(CURPOS(PIPE_A), pos); PIPE_A 10735 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE_FW(CURCNTR(PIPE_A), cntl); PIPE_A 10741 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE_FW(CURPOS(PIPE_A), pos); PIPE_A 10761 drivers/gpu/drm/i915/display/intel_display.c power_domain = POWER_DOMAIN_PIPE(PIPE_A); PIPE_A 10766 drivers/gpu/drm/i915/display/intel_display.c ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; PIPE_A 10768 drivers/gpu/drm/i915/display/intel_display.c *pipe = PIPE_A; PIPE_A 16365 drivers/gpu/drm/i915/display/intel_display.c WARN_ON(I915_READ(CURCNTR(PIPE_A)) & MCURSOR_MODE); PIPE_A 16431 drivers/gpu/drm/i915/display/intel_display.c (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A); PIPE_A 16637 drivers/gpu/drm/i915/display/intel_display.c enum pipe pipe = PIPE_A; PIPE_A 16887 drivers/gpu/drm/i915/display/intel_display.c (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A)) PIPE_A 16894 drivers/gpu/drm/i915/display/intel_display.c val |= SDVO_PIPE_SEL(PIPE_A); PIPE_A 16905 drivers/gpu/drm/i915/display/intel_display.c (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A)) PIPE_A 16912 drivers/gpu/drm/i915/display/intel_display.c val |= DP_PIPE_SEL(PIPE_A); PIPE_A 100 drivers/gpu/drm/i915/display/intel_display.h TRANSCODER_A = PIPE_A, PIPE_A 1027 drivers/gpu/drm/i915/display/intel_display_power.c if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0) PIPE_A 1028 drivers/gpu/drm/i915/display/intel_display_power.c i830_enable_pipe(dev_priv, PIPE_A); PIPE_A 1037 drivers/gpu/drm/i915/display/intel_display_power.c i830_disable_pipe(dev_priv, PIPE_A); PIPE_A 1043 drivers/gpu/drm/i915/display/intel_display_power.c return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE && PIPE_A 1184 drivers/gpu/drm/i915/display/intel_display_power.c if (pipe != PIPE_A) PIPE_A 1404 drivers/gpu/drm/i915/display/intel_display_power.c pipe = PIPE_A; PIPE_A 1464 drivers/gpu/drm/i915/display/intel_display_power.c assert_pll_disabled(dev_priv, PIPE_A); PIPE_A 1488 drivers/gpu/drm/i915/display/intel_display_power.c enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; PIPE_A 1611 drivers/gpu/drm/i915/display/intel_display_power.c enum pipe pipe = PIPE_A; PIPE_A 1641 drivers/gpu/drm/i915/display/intel_display_power.c enum pipe pipe = PIPE_A; PIPE_A 4765 drivers/gpu/drm/i915/display/intel_display_power.c u32 status = I915_READ(DPLL(PIPE_A)); PIPE_A 1329 drivers/gpu/drm/i915/display/intel_display_types.h case PIPE_A: PIPE_A 799 drivers/gpu/drm/i915/display/intel_dp.c unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); PIPE_A 853 drivers/gpu/drm/i915/display/intel_dp.c pipe = PIPE_A; PIPE_A 928 drivers/gpu/drm/i915/display/intel_dp.c for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { PIPE_A 3092 drivers/gpu/drm/i915/display/intel_dp.c *pipe = PIPE_A; PIPE_A 3494 drivers/gpu/drm/i915/display/intel_dp.c if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) PIPE_A 4102 drivers/gpu/drm/i915/display/intel_dp.c intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); PIPE_A 4103 drivers/gpu/drm/i915/display/intel_dp.c intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); PIPE_A 4107 drivers/gpu/drm/i915/display/intel_dp.c DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) | PIPE_A 4116 drivers/gpu/drm/i915/display/intel_dp.c intel_wait_for_vblank_if_active(dev_priv, PIPE_A); PIPE_A 4117 drivers/gpu/drm/i915/display/intel_dp.c intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); PIPE_A 4118 drivers/gpu/drm/i915/display/intel_dp.c intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); PIPE_A 7080 drivers/gpu/drm/i915/display/intel_dp.c if (pipe != PIPE_A && pipe != PIPE_B) PIPE_A 7083 drivers/gpu/drm/i915/display/intel_dp.c if (pipe != PIPE_A && pipe != PIPE_B) PIPE_A 7084 drivers/gpu/drm/i915/display/intel_dp.c pipe = PIPE_A; PIPE_A 133 drivers/gpu/drm/i915/display/intel_fifo_underrun.c u32 bit = (pipe == PIPE_A) ? PIPE_A 199 drivers/gpu/drm/i915/display/intel_fifo_underrun.c u32 bit = (pch_transcoder == PIPE_A) ? PIPE_A 2016 drivers/gpu/drm/i915/display/intel_hdmi.c intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); PIPE_A 2017 drivers/gpu/drm/i915/display/intel_hdmi.c intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); PIPE_A 2020 drivers/gpu/drm/i915/display/intel_hdmi.c temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); PIPE_A 2034 drivers/gpu/drm/i915/display/intel_hdmi.c intel_wait_for_vblank_if_active(dev_priv, PIPE_A); PIPE_A 2035 drivers/gpu/drm/i915/display/intel_hdmi.c intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); PIPE_A 2036 drivers/gpu/drm/i915/display/intel_hdmi.c intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); PIPE_A 572 drivers/gpu/drm/i915/display/intel_panel.c if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) PIPE_A 1734 drivers/gpu/drm/i915/display/intel_panel.c if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) PIPE_A 179 drivers/gpu/drm/i915/display/intel_pipe_crc.c case PIPE_A: PIPE_A 243 drivers/gpu/drm/i915/display/intel_pipe_crc.c case PIPE_A: PIPE_A 316 drivers/gpu/drm/i915/display/intel_pipe_crc.c pipe_config->base.active && crtc->pipe == PIPE_A && PIPE_A 1752 drivers/gpu/drm/i915/display/intel_sdvo.c intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); PIPE_A 1753 drivers/gpu/drm/i915/display/intel_sdvo.c intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); PIPE_A 1756 drivers/gpu/drm/i915/display/intel_sdvo.c temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); PIPE_A 1762 drivers/gpu/drm/i915/display/intel_sdvo.c intel_wait_for_vblank_if_active(dev_priv, PIPE_A); PIPE_A 1763 drivers/gpu/drm/i915/display/intel_sdvo.c intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); PIPE_A 1764 drivers/gpu/drm/i915/display/intel_sdvo.c intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); PIPE_A 2351 drivers/gpu/drm/i915/display/intel_sprite.c return pipe == PIPE_A && plane_id == PLANE_PRIMARY; PIPE_A 1016 drivers/gpu/drm/i915/display/vlv_dsi.c *pipe = port == PORT_A ? PIPE_A : PIPE_B; PIPE_A 1873 drivers/gpu/drm/i915/display/vlv_dsi.c intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); PIPE_A 1875 drivers/gpu/drm/i915/display/vlv_dsi.c intel_encoder->crtc_mask = BIT(PIPE_A); PIPE_A 1216 drivers/gpu/drm/i915/gvt/cmd_parser.c [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE}, PIPE_A 1218 drivers/gpu/drm/i915/gvt/cmd_parser.c [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE}, PIPE_A 1271 drivers/gpu/drm/i915/gvt/cmd_parser.c info->pipe = PIPE_A; PIPE_A 1284 drivers/gpu/drm/i915/gvt/cmd_parser.c info->pipe = PIPE_A; PIPE_A 46 drivers/gpu/drm/i915/gvt/display.c pipe = PIPE_A; PIPE_A 74 drivers/gpu/drm/i915/gvt/display.c if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES)) PIPE_A 344 drivers/gpu/drm/i915/gvt/display.c vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; PIPE_A 434 drivers/gpu/drm/i915/gvt/display.c [PIPE_A] = PIPE_A_VBLANK, PIPE_A 440 drivers/gpu/drm/i915/gvt/display.c if (pipe < PIPE_A || pipe > PIPE_C) PIPE_A 1959 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPEDSL(PIPE_A), D_ALL); PIPE_A 1964 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); PIPE_A 1969 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPESTAT(PIPE_A), D_ALL); PIPE_A 1974 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL); PIPE_A 1979 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL); PIPE_A 1984 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(CURCNTR(PIPE_A), D_ALL); PIPE_A 1988 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(CURPOS(PIPE_A), D_ALL); PIPE_A 1992 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(CURBASE(PIPE_A), D_ALL); PIPE_A 1996 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL); PIPE_A 2009 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPCNTR(PIPE_A), D_ALL); PIPE_A 2010 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPADDR(PIPE_A), D_ALL); PIPE_A 2011 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPSTRIDE(PIPE_A), D_ALL); PIPE_A 2012 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPPOS(PIPE_A), D_ALL); PIPE_A 2013 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPSIZE(PIPE_A), D_ALL); PIPE_A 2014 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); PIPE_A 2015 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPOFFSET(PIPE_A), D_ALL); PIPE_A 2016 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL); PIPE_A 2017 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL, PIPE_A 2042 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRCTL(PIPE_A), D_ALL); PIPE_A 2043 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRLINOFF(PIPE_A), D_ALL); PIPE_A 2044 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRSTRIDE(PIPE_A), D_ALL); PIPE_A 2045 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRPOS(PIPE_A), D_ALL); PIPE_A 2046 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRSIZE(PIPE_A), D_ALL); PIPE_A 2047 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRKEYVAL(PIPE_A), D_ALL); PIPE_A 2048 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRKEYMSK(PIPE_A), D_ALL); PIPE_A 2049 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); PIPE_A 2050 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRKEYMAX(PIPE_A), D_ALL); PIPE_A 2051 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPROFFSET(PIPE_A), D_ALL); PIPE_A 2052 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRSCALE(PIPE_A), D_ALL); PIPE_A 2053 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL); PIPE_A 2054 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL, PIPE_A 2162 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PF_CTL(PIPE_A), D_ALL); PIPE_A 2163 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL); PIPE_A 2164 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PF_WIN_POS(PIPE_A), D_ALL); PIPE_A 2165 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PF_VSCALE(PIPE_A), D_ALL); PIPE_A 2166 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PF_HSCALE(PIPE_A), D_ALL); PIPE_A 2214 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); PIPE_A 2217 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); PIPE_A 2220 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); PIPE_A 2249 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL); PIPE_A 2253 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL); PIPE_A 2254 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL); PIPE_A 2255 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL); PIPE_A 2334 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL); PIPE_A 2335 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL); PIPE_A 2336 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL); PIPE_A 2337 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL); PIPE_A 2338 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL); PIPE_A 2339 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL); PIPE_A 2340 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL); PIPE_A 2341 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL); PIPE_A 2342 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL); PIPE_A 2343 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL); PIPE_A 2344 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL); PIPE_A 2345 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL); PIPE_A 2346 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL); PIPE_A 2376 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL); PIPE_A 2377 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL); PIPE_A 2378 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); PIPE_A 2400 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL); PIPE_A 2426 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GAMMA_MODE(PIPE_A), D_ALL); PIPE_A 2430 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPE_MULT(PIPE_A), D_ALL); PIPE_A 2471 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL); PIPE_A 2473 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL); PIPE_A 2699 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, PIPE_A 2701 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, PIPE_A 2703 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, PIPE_A 2705 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS); PIPE_A 2771 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS); PIPE_A 2794 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS); PIPE_A 2908 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); PIPE_A 2909 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); PIPE_A 2915 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); PIPE_A 2916 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); PIPE_A 2922 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); PIPE_A 2923 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); PIPE_A 2929 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); PIPE_A 2930 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); PIPE_A 2931 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); PIPE_A 2932 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); PIPE_A 2944 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL); PIPE_A 2948 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); PIPE_A 2949 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); PIPE_A 2950 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); PIPE_A 2960 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); PIPE_A 2964 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); PIPE_A 2965 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); PIPE_A 2966 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); PIPE_A 2976 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL); PIPE_A 2980 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); PIPE_A 2981 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); PIPE_A 2982 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); PIPE_A 2983 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); PIPE_A 2995 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); PIPE_A 2996 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); PIPE_A 2997 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); PIPE_A 2998 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); PIPE_A 3010 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); PIPE_A 3011 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); PIPE_A 3012 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); PIPE_A 3013 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); PIPE_A 3086 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS); PIPE_A 3089 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS); PIPE_A 3092 drivers/gpu/drm/i915/gvt/handlers.c MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS); PIPE_A 3332 drivers/gpu/drm/i915/gvt/handlers.c {D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL}, PIPE_A 449 drivers/gpu/drm/i915/gvt/interrupt.c DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_a, GEN8_DE_PIPE_ISR(PIPE_A)); PIPE_A 72 drivers/gpu/drm/i915/gvt/reg.h (((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \ PIPE_A 82 drivers/gpu/drm/i915/gvt/reg.h (((reg) == 0x50080 || (reg) == 0x50090) ? (PIPE_A) : \ PIPE_A 701 drivers/gpu/drm/i915/i915_irq.c i915_enable_pipestat(dev_priv, PIPE_A, PIPE_A 1744 drivers/gpu/drm/i915/i915_irq.c case PIPE_A: PIPE_A 2179 drivers/gpu/drm/i915/i915_irq.c intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); PIPE_A 3192 drivers/gpu/drm/i915/i915_irq.c i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); PIPE_A 3931 drivers/gpu/drm/i915/i915_irq.c i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); PIPE_A 4105 drivers/gpu/drm/i915/i915_irq.c i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); PIPE_A 4222 drivers/gpu/drm/i915/i915_irq.c i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); PIPE_A 4223 drivers/gpu/drm/i915/i915_irq.c i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); PIPE_A 98 drivers/gpu/drm/i915/i915_pci.c [PIPE_A] = CURSOR_A_OFFSET, \ PIPE_A 103 drivers/gpu/drm/i915/i915_pci.c [PIPE_A] = CURSOR_A_OFFSET, \ PIPE_A 109 drivers/gpu/drm/i915/i915_pci.c [PIPE_A] = CURSOR_A_OFFSET, \ PIPE_A 116 drivers/gpu/drm/i915/i915_pci.c [PIPE_A] = CURSOR_A_OFFSET, \ PIPE_A 252 drivers/gpu/drm/i915/i915_reg.h INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \ PIPE_A 259 drivers/gpu/drm/i915/i915_reg.h INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \ PIPE_A 8292 drivers/gpu/drm/i915/i915_reg.h #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */ PIPE_A 44 drivers/gpu/drm/i915/i915_trace.h __entry->frame[PIPE_A], __entry->scanline[PIPE_A], PIPE_A 71 drivers/gpu/drm/i915/i915_trace.h __entry->frame[PIPE_A], __entry->scanline[PIPE_A], PIPE_A 168 drivers/gpu/drm/i915/i915_trace.h __entry->frame[PIPE_A], __entry->scanline[PIPE_A], PIPE_A 869 drivers/gpu/drm/i915/intel_device_info.c runtime->num_scalers[PIPE_A] = 2; PIPE_A 892 drivers/gpu/drm/i915/intel_device_info.c runtime->num_sprites[PIPE_A] = 2; PIPE_A 936 drivers/gpu/drm/i915/intel_device_info.c enabled_mask &= ~BIT(PIPE_A); PIPE_A 503 drivers/gpu/drm/i915/intel_pm.c case PIPE_A: PIPE_A 961 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); PIPE_A 967 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | PIPE_A 968 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); PIPE_A 1011 drivers/gpu/drm/i915/intel_pm.c FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); PIPE_A 1013 drivers/gpu/drm/i915/intel_pm.c FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) | PIPE_A 1014 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | PIPE_A 1015 drivers/gpu/drm/i915/intel_pm.c FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); PIPE_A 1037 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) | PIPE_A 1038 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) | PIPE_A 1039 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI)); PIPE_A 1049 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) | PIPE_A 1050 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) | PIPE_A 1051 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI)); PIPE_A 1992 drivers/gpu/drm/i915/intel_pm.c case PIPE_A: PIPE_A 3562 drivers/gpu/drm/i915/intel_pm.c if (dirty & WM_DIRTY_PIPE(PIPE_A)) PIPE_A 3569 drivers/gpu/drm/i915/intel_pm.c if (dirty & WM_DIRTY_LINETIME(PIPE_A)) PIPE_A 3570 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); PIPE_A 5837 drivers/gpu/drm/i915/intel_pm.c [PIPE_A] = WM0_PIPEA_ILK, PIPE_A 5893 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA); PIPE_A 5900 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA); PIPE_A 5901 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA); PIPE_A 5933 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA); PIPE_A 5936 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB); PIPE_A 5937 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA); PIPE_A 5938 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA); PIPE_A 5964 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8; PIPE_A 5965 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8; PIPE_A 5966 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8; PIPE_A 5977 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8; PIPE_A 5978 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8; PIPE_A 5979 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8; PIPE_A 9147 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(TRANS_CHICKEN1(PIPE_A), PIPE_A 9148 drivers/gpu/drm/i915/intel_pm.c I915_READ(TRANS_CHICKEN1(PIPE_A)) | PIPE_A 482 drivers/video/fbdev/intelfb/intelfbhw.c if (unlikely(pipe == PIPE_A)) PIPE_A 483 drivers/video/fbdev/intelfb/intelfbhw.c return PIPE_A; PIPE_A 488 drivers/video/fbdev/intelfb/intelfbhw.c if (likely(pipe == PIPE_A)) PIPE_A 489 drivers/video/fbdev/intelfb/intelfbhw.c return PIPE_A; PIPE_A 494 drivers/video/fbdev/intelfb/intelfbhw.c pipe = PIPE_A; PIPE_A 503 drivers/video/fbdev/intelfb/intelfbhw.c u32 palette_reg = (dinfo->pipe == PIPE_A) ?