PIPECONF          896 drivers/gpu/drm/i915/display/icl_dsi.c 		tmp = I915_READ(PIPECONF(dsi_trans));
PIPECONF          898 drivers/gpu/drm/i915/display/icl_dsi.c 		I915_WRITE(PIPECONF(dsi_trans), tmp);
PIPECONF          901 drivers/gpu/drm/i915/display/icl_dsi.c 		if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans),
PIPECONF         1076 drivers/gpu/drm/i915/display/icl_dsi.c 		tmp = I915_READ(PIPECONF(dsi_trans));
PIPECONF         1078 drivers/gpu/drm/i915/display/icl_dsi.c 		I915_WRITE(PIPECONF(dsi_trans), tmp);
PIPECONF         1081 drivers/gpu/drm/i915/display/icl_dsi.c 		if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans),
PIPECONF         1333 drivers/gpu/drm/i915/display/icl_dsi.c 		tmp = I915_READ(PIPECONF(dsi_trans));
PIPECONF          432 drivers/gpu/drm/i915/display/intel_color.c 	val = I915_READ(PIPECONF(pipe));
PIPECONF          435 drivers/gpu/drm/i915/display/intel_color.c 	I915_WRITE(PIPECONF(pipe), val);
PIPECONF          445 drivers/gpu/drm/i915/display/intel_color.c 	val = I915_READ(PIPECONF(pipe));
PIPECONF          448 drivers/gpu/drm/i915/display/intel_color.c 	I915_WRITE(PIPECONF(pipe), val);
PIPECONF          661 drivers/gpu/drm/i915/display/intel_crt.c 	pipeconf_reg = PIPECONF(pipe);
PIPECONF         1077 drivers/gpu/drm/i915/display/intel_display.c 		i915_reg_t reg = PIPECONF(cpu_transcoder);
PIPECONF         1258 drivers/gpu/drm/i915/display/intel_display.c 		u32 val = I915_READ(PIPECONF(cpu_transcoder));
PIPECONF         1646 drivers/gpu/drm/i915/display/intel_display.c 	pipeconf_val = I915_READ(PIPECONF(pipe));
PIPECONF         1692 drivers/gpu/drm/i915/display/intel_display.c 	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
PIPECONF         1829 drivers/gpu/drm/i915/display/intel_display.c 	reg = PIPECONF(cpu_transcoder);
PIPECONF         1870 drivers/gpu/drm/i915/display/intel_display.c 	reg = PIPECONF(cpu_transcoder);
PIPECONF         4844 drivers/gpu/drm/i915/display/intel_display.c 	temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
PIPECONF         4916 drivers/gpu/drm/i915/display/intel_display.c 	temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
PIPECONF         4944 drivers/gpu/drm/i915/display/intel_display.c 	temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
PIPECONF         5270 drivers/gpu/drm/i915/display/intel_display.c 		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
PIPECONF         8234 drivers/gpu/drm/i915/display/intel_display.c 	if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
PIPECONF         8289 drivers/gpu/drm/i915/display/intel_display.c 		pipeconf |= I915_READ(PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
PIPECONF         8334 drivers/gpu/drm/i915/display/intel_display.c 	I915_WRITE(PIPECONF(crtc->pipe), pipeconf);
PIPECONF         8335 drivers/gpu/drm/i915/display/intel_display.c 	POSTING_READ(PIPECONF(crtc->pipe));
PIPECONF         8786 drivers/gpu/drm/i915/display/intel_display.c 	tmp = I915_READ(PIPECONF(crtc->pipe));
PIPECONF         9427 drivers/gpu/drm/i915/display/intel_display.c 	I915_WRITE(PIPECONF(pipe), val);
PIPECONF         9428 drivers/gpu/drm/i915/display/intel_display.c 	POSTING_READ(PIPECONF(pipe));
PIPECONF         9446 drivers/gpu/drm/i915/display/intel_display.c 	I915_WRITE(PIPECONF(cpu_transcoder), val);
PIPECONF         9447 drivers/gpu/drm/i915/display/intel_display.c 	POSTING_READ(PIPECONF(cpu_transcoder));
PIPECONF         9962 drivers/gpu/drm/i915/display/intel_display.c 	tmp = I915_READ(PIPECONF(crtc->pipe));
PIPECONF         10291 drivers/gpu/drm/i915/display/intel_display.c 	tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
PIPECONF         16349 drivers/gpu/drm/i915/display/intel_display.c 	I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
PIPECONF         16350 drivers/gpu/drm/i915/display/intel_display.c 	POSTING_READ(PIPECONF(pipe));
PIPECONF         16368 drivers/gpu/drm/i915/display/intel_display.c 	I915_WRITE(PIPECONF(pipe), 0);
PIPECONF         16369 drivers/gpu/drm/i915/display/intel_display.c 	POSTING_READ(PIPECONF(pipe));
PIPECONF         16444 drivers/gpu/drm/i915/display/intel_display.c 		i915_reg_t reg = PIPECONF(cpu_transcoder);
PIPECONF         17282 drivers/gpu/drm/i915/display/intel_display.c 		error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
PIPECONF         1027 drivers/gpu/drm/i915/display/intel_display_power.c 	if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0)
PIPECONF         1029 drivers/gpu/drm/i915/display/intel_display_power.c 	if ((I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0)
PIPECONF         1043 drivers/gpu/drm/i915/display/intel_display_power.c 	return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE &&
PIPECONF         1044 drivers/gpu/drm/i915/display/intel_display_power.c 		I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
PIPECONF         6704 drivers/gpu/drm/i915/display/intel_dp.c 		i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
PIPECONF          992 drivers/gpu/drm/i915/display/vlv_dsi.c 			enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
PIPECONF           62 drivers/gpu/drm/i915/gvt/display.c 	if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))
PIPECONF           77 drivers/gpu/drm/i915/gvt/display.c 	if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)
PIPECONF          344 drivers/gpu/drm/i915/gvt/display.c 	vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
PIPECONF         1964 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
PIPECONF         1965 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
PIPECONF         1966 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
PIPECONF         1967 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);