PIPE0_DMIF_BUFFER_CONTROL  627 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
PIPE0_DMIF_BUFFER_CONTROL  632 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
PIPE0_DMIF_BUFFER_CONTROL  653 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
PIPE0_DMIF_BUFFER_CONTROL  658 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
PIPE0_DMIF_BUFFER_CONTROL  183 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\
PIPE0_DMIF_BUFFER_CONTROL  184 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 	SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh)
PIPE0_DMIF_BUFFER_CONTROL 8858 drivers/gpu/drm/radeon/cik.c 	WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
PIPE0_DMIF_BUFFER_CONTROL 8861 drivers/gpu/drm/radeon/cik.c 		if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
PIPE0_DMIF_BUFFER_CONTROL 1870 drivers/gpu/drm/radeon/evergreen.c 		WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
PIPE0_DMIF_BUFFER_CONTROL 1873 drivers/gpu/drm/radeon/evergreen.c 			if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
PIPE0_DMIF_BUFFER_CONTROL 2007 drivers/gpu/drm/radeon/si.c 	WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
PIPE0_DMIF_BUFFER_CONTROL 2010 drivers/gpu/drm/radeon/si.c 		if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &