PIC_IMR           167 arch/mips/sni/rm200.c 		writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
PIC_IMR           169 arch/mips/sni/rm200.c 		writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
PIC_IMR           182 arch/mips/sni/rm200.c 		writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
PIC_IMR           184 arch/mips/sni/rm200.c 		writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
PIC_IMR           239 arch/mips/sni/rm200.c 		readb(rm200_pic_slave + PIC_IMR);
PIC_IMR           240 arch/mips/sni/rm200.c 		writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
PIC_IMR           244 arch/mips/sni/rm200.c 		readb(rm200_pic_master + PIC_IMR);
PIC_IMR           245 arch/mips/sni/rm200.c 		writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
PIC_IMR           337 arch/mips/sni/rm200.c 	writeb(0xff, rm200_pic_master + PIC_IMR);
PIC_IMR           338 arch/mips/sni/rm200.c 	writeb(0xff, rm200_pic_slave + PIC_IMR);
PIC_IMR           341 arch/mips/sni/rm200.c 	writeb(0, rm200_pic_master + PIC_IMR);
PIC_IMR           342 arch/mips/sni/rm200.c 	writeb(1U << PIC_CASCADE_IR, rm200_pic_master + PIC_IMR);
PIC_IMR           343 arch/mips/sni/rm200.c 	writeb(MASTER_ICW4_DEFAULT, rm200_pic_master + PIC_IMR);
PIC_IMR           345 arch/mips/sni/rm200.c 	writeb(8, rm200_pic_slave + PIC_IMR);
PIC_IMR           346 arch/mips/sni/rm200.c 	writeb(PIC_CASCADE_IR, rm200_pic_slave + PIC_IMR);
PIC_IMR           347 arch/mips/sni/rm200.c 	writeb(SLAVE_ICW4_DEFAULT, rm200_pic_slave + PIC_IMR);
PIC_IMR           350 arch/mips/sni/rm200.c 	writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
PIC_IMR           351 arch/mips/sni/rm200.c 	writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);