PIC_CMD           139 arch/mips/sni/rm200.c #define PIC_ISR	   PIC_CMD
PIC_CMD           194 arch/mips/sni/rm200.c 		writeb(0x0B, rm200_pic_master + PIC_CMD);
PIC_CMD           195 arch/mips/sni/rm200.c 		value = readb(rm200_pic_master + PIC_CMD) & irqmask;
PIC_CMD           196 arch/mips/sni/rm200.c 		writeb(0x0A, rm200_pic_master + PIC_CMD);
PIC_CMD           199 arch/mips/sni/rm200.c 	writeb(0x0B, rm200_pic_slave + PIC_CMD); /* ISR register */
PIC_CMD           200 arch/mips/sni/rm200.c 	value = readb(rm200_pic_slave + PIC_CMD) & (irqmask >> 8);
PIC_CMD           201 arch/mips/sni/rm200.c 	writeb(0x0A, rm200_pic_slave + PIC_CMD);
PIC_CMD           241 arch/mips/sni/rm200.c 		writeb(0x60+(irq & 7), rm200_pic_slave + PIC_CMD);
PIC_CMD           242 arch/mips/sni/rm200.c 		writeb(0x60+PIC_CASCADE_IR, rm200_pic_master + PIC_CMD);
PIC_CMD           246 arch/mips/sni/rm200.c 		writeb(0x60+irq, rm200_pic_master + PIC_CMD);
PIC_CMD           302 arch/mips/sni/rm200.c 	writeb(0x0C, rm200_pic_master + PIC_CMD);	/* prepare for poll */
PIC_CMD           303 arch/mips/sni/rm200.c 	irq = readb(rm200_pic_master + PIC_CMD) & 7;
PIC_CMD           309 arch/mips/sni/rm200.c 		writeb(0x0C, rm200_pic_slave + PIC_CMD); /* prepare for poll */
PIC_CMD           310 arch/mips/sni/rm200.c 		irq = (readb(rm200_pic_slave + PIC_CMD) & 7) + 8;
PIC_CMD           340 arch/mips/sni/rm200.c 	writeb(0x11, rm200_pic_master + PIC_CMD);
PIC_CMD           344 arch/mips/sni/rm200.c 	writeb(0x11, rm200_pic_slave + PIC_CMD);