PHY_OFF            66 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define UFS_PHY_PHY_START			PHY_OFF(0x00)
PHY_OFF            67 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define UFS_PHY_POWER_DOWN_CONTROL		PHY_OFF(0x04)
PHY_OFF            68 drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.h #define UFS_PHY_PCS_READY_STATUS		PHY_OFF(0x168)
PHY_OFF            65 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_PHY_START			PHY_OFF(0x00)
PHY_OFF            66 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_POWER_DOWN_CONTROL		PHY_OFF(0x4)
PHY_OFF            67 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_TX_LANE_ENABLE			PHY_OFF(0x44)
PHY_OFF            68 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_PWM_G1_CLK_DIVIDER		PHY_OFF(0x08)
PHY_OFF            69 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_PWM_G2_CLK_DIVIDER		PHY_OFF(0x0C)
PHY_OFF            70 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_PWM_G3_CLK_DIVIDER		PHY_OFF(0x10)
PHY_OFF            71 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_PWM_G4_CLK_DIVIDER		PHY_OFF(0x14)
PHY_OFF            72 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_CORECLK_PWM_G1_CLK_DIVIDER	PHY_OFF(0x34)
PHY_OFF            73 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_CORECLK_PWM_G2_CLK_DIVIDER	PHY_OFF(0x38)
PHY_OFF            74 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_CORECLK_PWM_G3_CLK_DIVIDER	PHY_OFF(0x3C)
PHY_OFF            75 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_CORECLK_PWM_G4_CLK_DIVIDER	PHY_OFF(0x40)
PHY_OFF            76 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_OMC_STATUS_RDVAL		PHY_OFF(0x68)
PHY_OFF            77 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_LINE_RESET_TIME			PHY_OFF(0x28)
PHY_OFF            78 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_LINE_RESET_GRANULARITY		PHY_OFF(0x2C)
PHY_OFF            79 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_TSYNC_RSYNC_CNTL		PHY_OFF(0x48)
PHY_OFF            80 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_PLL_CNTL			PHY_OFF(0x50)
PHY_OFF            81 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_TX_LARGE_AMP_DRV_LVL		PHY_OFF(0x54)
PHY_OFF            82 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_TX_SMALL_AMP_DRV_LVL		PHY_OFF(0x5C)
PHY_OFF            83 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_TX_LARGE_AMP_POST_EMP_LVL	PHY_OFF(0x58)
PHY_OFF            84 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_TX_SMALL_AMP_POST_EMP_LVL	PHY_OFF(0x60)
PHY_OFF            85 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_CFG_CHANGE_CNT_VAL		PHY_OFF(0x64)
PHY_OFF            86 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_RX_SYNC_WAIT_TIME		PHY_OFF(0x6C)
PHY_OFF            87 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_TX_MIN_SLEEP_NOCONFIG_TIME_CAPABILITY	PHY_OFF(0xB4)
PHY_OFF            88 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_RX_MIN_SLEEP_NOCONFIG_TIME_CAPABILITY	PHY_OFF(0xE0)
PHY_OFF            89 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_TX_MIN_STALL_NOCONFIG_TIME_CAPABILITY	PHY_OFF(0xB8)
PHY_OFF            90 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAPABILITY	PHY_OFF(0xE4)
PHY_OFF            91 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_TX_MIN_SAVE_CONFIG_TIME_CAPABILITY	PHY_OFF(0xBC)
PHY_OFF            92 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_RX_MIN_SAVE_CONFIG_TIME_CAPABILITY	PHY_OFF(0xE8)
PHY_OFF            93 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_RX_PWM_BURST_CLOSURE_LENGTH_CAPABILITY	PHY_OFF(0xFC)
PHY_OFF            94 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_RX_MIN_ACTIVATETIME_CAPABILITY		PHY_OFF(0x100)
PHY_OFF            95 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_RX_SIGDET_CTRL3				PHY_OFF(0x14c)
PHY_OFF            96 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_RMMI_ATTR_CTRL			PHY_OFF(0x160)
PHY_OFF           105 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_RMMI_ATTRID			PHY_OFF(0x164)
PHY_OFF           106 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_RMMI_ATTRWRVAL			PHY_OFF(0x168)
PHY_OFF           107 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_RMMI_ATTRRDVAL_L0_STATUS	PHY_OFF(0x16C)
PHY_OFF           108 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_RMMI_ATTRRDVAL_L1_STATUS	PHY_OFF(0x170)
PHY_OFF           109 drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.h #define UFS_PHY_PCS_READY_STATUS		PHY_OFF(0x174)