PHYACC_ATTR_MODE_WRITE   57 drivers/net/phy/microchip_t1.c 	if (mode > PHYACC_ATTR_MODE_WRITE || bank > PHYACC_ATTR_BANK_MAX)
PHYACC_ATTR_MODE_WRITE   61 drivers/net/phy/microchip_t1.c 		if (mode == PHYACC_ATTR_MODE_WRITE)
PHYACC_ATTR_MODE_WRITE   68 drivers/net/phy/microchip_t1.c 	if (mode == PHYACC_ATTR_MODE_WRITE) {
PHYACC_ATTR_MODE_WRITE  102 drivers/net/phy/microchip_t1.c 	rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, bank, offset, new);
PHYACC_ATTR_MODE_WRITE  123 drivers/net/phy/microchip_t1.c 		{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_PCS, 0x20,
PHYACC_ATTR_MODE_WRITE  126 drivers/net/phy/microchip_t1.c 		{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_MISC, 0x21,
PHYACC_ATTR_MODE_WRITE  131 drivers/net/phy/microchip_t1.c 		{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_MISC, 0x20,
PHYACC_ATTR_MODE_WRITE  136 drivers/net/phy/microchip_t1.c 		{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_MISC, 0x24,