PHASE             915 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		REG_WRITE(PHASE[inst], clock_100hz);
PHASE             994 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		clock_hz = REG_READ(PHASE[inst]);
PHASE              61 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRII(PHASE, DP_DTO, 0),\
PHASE              62 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRII(PHASE, DP_DTO, 1),\
PHASE              63 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRII(PHASE, DP_DTO, 2),\
PHASE              64 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRII(PHASE, DP_DTO, 3),\
PHASE              65 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRII(PHASE, DP_DTO, 4),\
PHASE              66 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRII(PHASE, DP_DTO, 5),\
PHASE              84 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRII(PHASE, DP_DTO, 0),\
PHASE              85 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRII(PHASE, DP_DTO, 1),\
PHASE              86 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRII(PHASE, DP_DTO, 2),\
PHASE              87 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRII(PHASE, DP_DTO, 3),\
PHASE             110 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRII(PHASE, DP_DTO, 0),\
PHASE             111 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRII(PHASE, DP_DTO, 1),\
PHASE             112 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRII(PHASE, DP_DTO, 2),\
PHASE             113 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 		SRII(PHASE, DP_DTO, 3),\
PHASE             158 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 	uint32_t PHASE[MAX_PIPES];
PHASE            1835 drivers/scsi/FlashPoint.c 			       && !((RDW_HARPOON((ioport + hp_intstat)) & PHASE)
PHASE            1862 drivers/scsi/FlashPoint.c 				    (PROG_HLT | RSEL | PHASE | BUS_FREE));
PHASE            1898 drivers/scsi/FlashPoint.c 				    (PHASE | IUNKWN | PROG_HLT));
PHASE            2086 drivers/scsi/FlashPoint.c 			    (PROG_HLT | TIMEOUT | SEL | BUS_FREE | PHASE |
PHASE            2674 drivers/scsi/FlashPoint.c 				WRW_HARPOON((port + hp_intstat), PHASE);
PHASE            2679 drivers/scsi/FlashPoint.c 		WRW_HARPOON((port + hp_intstat), PHASE);
PHASE            2752 drivers/scsi/FlashPoint.c 				(PHASE | RESET))
PHASE            2834 drivers/scsi/FlashPoint.c 	while (!(RDW_HARPOON((port + hp_intstat)) & (PHASE | RESET)) &&
PHASE            2844 drivers/scsi/FlashPoint.c 			WRW_HARPOON((port + hp_intstat), PHASE);
PHASE            2849 drivers/scsi/FlashPoint.c 	WRW_HARPOON((port + hp_intstat), PHASE);
PHASE            2852 drivers/scsi/FlashPoint.c 			    (BUS_FREE | PHASE | XFER_CNT_0));
PHASE            2868 drivers/scsi/FlashPoint.c 				(BUS_FREE | PHASE))) {
PHASE            4224 drivers/scsi/FlashPoint.c 	WRW_HARPOON((port + hp_intstat), (BUS_FREE | PHASE | XFER_CNT_0));
PHASE            4239 drivers/scsi/FlashPoint.c 		while (!(RDW_HARPOON((port + hp_intstat)) & (BUS_FREE | PHASE))) {
PHASE            6151 drivers/scsi/FlashPoint.c 			    (RESET | TIMEOUT | SEL | BUS_FREE | PHASE));