PERF_CSTATE_CORE_C3_RES 173 arch/x86/events/intel/cstate.c [PERF_CSTATE_CORE_C3_RES] = { MSR_CORE_C3_RESIDENCY, &group_cstate_core_c3, test_msr }, PERF_CSTATE_CORE_C3_RES 505 arch/x86/events/intel/cstate.c .core_events = BIT(PERF_CSTATE_CORE_C3_RES) | PERF_CSTATE_CORE_C3_RES 514 arch/x86/events/intel/cstate.c .core_events = BIT(PERF_CSTATE_CORE_C3_RES) | PERF_CSTATE_CORE_C3_RES 525 arch/x86/events/intel/cstate.c .core_events = BIT(PERF_CSTATE_CORE_C3_RES) | PERF_CSTATE_CORE_C3_RES 540 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_CORE_C3_RES) | PERF_CSTATE_CORE_C3_RES 587 arch/x86/events/intel/cstate.c BIT(PERF_CSTATE_CORE_C3_RES) |