PENDING           599 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c 	cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save);
PENDING           600 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c 	cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save);
PENDING           603 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c 	cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load);
PENDING           604 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c 	cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load);
PENDING           651 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c 	cp_bra (ctx, USER_SAVE, PENDING, cp_exit);
PENDING           182 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save);
PENDING           183 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save);
PENDING           186 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load);
PENDING           187 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load);
PENDING           209 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	cp_wait(ctx, INTR, PENDING);
PENDING           241 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	cp_bra (ctx, USER_SAVE, PENDING, cp_exit);
PENDING           197 drivers/xen/events/events_fifo.c 	sync_clear_bit(EVTCHN_FIFO_BIT(PENDING, word), BM(word));
PENDING           203 drivers/xen/events/events_fifo.c 	sync_set_bit(EVTCHN_FIFO_BIT(PENDING, word), BM(word));
PENDING           209 drivers/xen/events/events_fifo.c 	return sync_test_bit(EVTCHN_FIFO_BIT(PENDING, word), BM(word));
PENDING            87 include/asm-generic/qspinlock_types.h #define _Q_PENDING_MASK		_Q_SET_MASK(PENDING)
PENDING           157 kernel/signal.c 	    PENDING(&t->pending, &t->blocked) ||
PENDING           158 kernel/signal.c 	    PENDING(&t->signal->shared_pending, &t->blocked) ||