PCI_BASE_ADDRESS_0   84 arch/arm/kernel/bios32.c 	pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY);
PCI_BASE_ADDRESS_0  218 arch/arm/kernel/bios32.c 		pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
PCI_BASE_ADDRESS_0  366 arch/arm/mach-ixp4xx/common-pci.c 		local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET);
PCI_BASE_ADDRESS_0  318 arch/mips/pci/pci-ar2315.c 	ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_0,
PCI_BASE_ADDRESS_0  149 arch/mips/pci/pci-ar724x.c 	if (where == PCI_BASE_ADDRESS_0 && size == 4 &&
PCI_BASE_ADDRESS_0  175 arch/mips/pci/pci-ar724x.c 	if (soc_is_ar7240() && where == PCI_BASE_ADDRESS_0 && size == 4) {
PCI_BASE_ADDRESS_0   52 arch/mips/pci/pci-emma2rh.c 	emma2rh_out32(EMMA2RH_PCI_CONFIG_BASE + PCI_BASE_ADDRESS_0, 0x10000000);
PCI_BASE_ADDRESS_0  369 arch/mips/pci/pci-mt7620.c 		pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4,
PCI_BASE_ADDRESS_0  371 arch/mips/pci/pci-mt7620.c 		pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
PCI_BASE_ADDRESS_0  191 arch/mips/pci/pci-rt2880.c 		rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
PCI_BASE_ADDRESS_0  192 arch/mips/pci/pci-rt2880.c 		(void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
PCI_BASE_ADDRESS_0  243 arch/mips/pci/pci-rt2880.c 	rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
PCI_BASE_ADDRESS_0  244 arch/mips/pci/pci-rt2880.c 	(void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
PCI_BASE_ADDRESS_0  541 arch/mips/pci/pci-rt3883.c 				       PCI_BASE_ADDRESS_0,
PCI_BASE_ADDRESS_0  545 arch/mips/pci/pci-rt3883.c 				      PCI_BASE_ADDRESS_0);
PCI_BASE_ADDRESS_0  150 arch/powerpc/kernel/pci_of_scan.c 		if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
PCI_BASE_ADDRESS_0  151 arch/powerpc/kernel/pci_of_scan.c 			res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
PCI_BASE_ADDRESS_0 1873 arch/powerpc/platforms/4xx/pci.c 		out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(ep_addr));
PCI_BASE_ADDRESS_0 1901 arch/powerpc/platforms/4xx/pci.c 		out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(res->start));
PCI_BASE_ADDRESS_0  344 arch/powerpc/platforms/chrp/pci.c 		pci_write_config_dword(sl82c105, PCI_BASE_ADDRESS_0, 0);
PCI_BASE_ADDRESS_0  236 arch/powerpc/platforms/maple/pci.c 	if (offset >= PCI_BASE_ADDRESS_0 && offset < PCI_CAPABILITY_LIST)
PCI_BASE_ADDRESS_0 1128 arch/powerpc/platforms/powermac/pci.c 			pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0);
PCI_BASE_ADDRESS_0 1154 arch/powerpc/platforms/powermac/pci.c 			pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i,
PCI_BASE_ADDRESS_0 1164 arch/powerpc/platforms/powermac/pci.c 			pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i,
PCI_BASE_ADDRESS_0  299 arch/powerpc/sysdev/fsl_pci.c 	early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
PCI_BASE_ADDRESS_0  300 arch/powerpc/sysdev/fsl_pci.c 	early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
PCI_BASE_ADDRESS_0  308 arch/powerpc/sysdev/fsl_pci.c 	early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
PCI_BASE_ADDRESS_0  916 arch/powerpc/sysdev/fsl_pci.c 			PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
PCI_BASE_ADDRESS_0  376 arch/sh/drivers/pci/pci-sh7780.c 	__raw_writel(0, chan->reg_base + PCI_BASE_ADDRESS_0);
PCI_BASE_ADDRESS_0  442 arch/sparc/kernel/leon_pci_grpci1.c 	grpci1_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
PCI_BASE_ADDRESS_0  443 arch/sparc/kernel/leon_pci_grpci1.c 	grpci1_cfg_r32(priv, TGT, 0, PCI_BASE_ADDRESS_0, &bar_sz);
PCI_BASE_ADDRESS_0  446 arch/sparc/kernel/leon_pci_grpci1.c 	grpci1_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0, pciadr);
PCI_BASE_ADDRESS_0  634 arch/sparc/kernel/leon_pci_grpci2.c 		grpci2_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0+i*4, pciadr);
PCI_BASE_ADDRESS_0  233 arch/sparc/kernel/pci.c 		if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
PCI_BASE_ADDRESS_0  234 arch/sparc/kernel/pci.c 			res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
PCI_BASE_ADDRESS_0  435 arch/sparc/kernel/pcic.c 	       pcic->pcic_regs+PCI_BASE_ADDRESS_0);
PCI_BASE_ADDRESS_0  645 arch/x86/kernel/early-quirks.c 	addr  =      read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0);
PCI_BASE_ADDRESS_0  267 arch/x86/kernel/early_printk.c 	bar0 = read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0);
PCI_BASE_ADDRESS_0   33 arch/x86/kernel/vsmp_64.c 	cfg = read_pci_config(0, 0x1f, 0, PCI_BASE_ADDRESS_0);
PCI_BASE_ADDRESS_0  111 arch/x86/kernel/vsmp_64.c 	cfg = read_pci_config(0, 0x1f, 0, PCI_BASE_ADDRESS_0);
PCI_BASE_ADDRESS_0  182 arch/x86/pci/ce4100.c 	case PCI_BASE_ADDRESS_0:
PCI_BASE_ADDRESS_0  183 arch/x86/pci/ce4100.c 	case PCI_BASE_ADDRESS_0 + 1:
PCI_BASE_ADDRESS_0  184 arch/x86/pci/ce4100.c 	case PCI_BASE_ADDRESS_0 + 2:
PCI_BASE_ADDRESS_0  185 arch/x86/pci/ce4100.c 	case PCI_BASE_ADDRESS_0 + 3:
PCI_BASE_ADDRESS_0  205 arch/x86/pci/ce4100.c 				PCI_BASE_ADDRESS_0, 4, &av_bridge_base);
PCI_BASE_ADDRESS_0  307 arch/x86/pci/ce4100.c 	    ((reg & ~3) == PCI_BASE_ADDRESS_0))
PCI_BASE_ADDRESS_0  461 arch/x86/pci/fixup.c 	pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
PCI_BASE_ADDRESS_0   99 arch/x86/pci/intel_mid_pci.c 	int bar = (reg - PCI_BASE_ADDRESS_0) >> 2;
PCI_BASE_ADDRESS_0  197 arch/x86/pci/intel_mid_pci.c 	    (where >= PCI_BASE_ADDRESS_0 && where <= PCI_BASE_ADDRESS_5)) {
PCI_BASE_ADDRESS_0   68 arch/xtensa/lib/pci-auto.c 	for (bar = PCI_BASE_ADDRESS_0, bar_nr = 0;
PCI_BASE_ADDRESS_0  243 drivers/firewire/init_ohci1394_dma.c 	ohci_base = read_pci_config(num, slot, func, PCI_BASE_ADDRESS_0+(0<<2))
PCI_BASE_ADDRESS_0   52 drivers/gpu/drm/i915/gvt/cfg_space.c 	[PCI_BASE_ADDRESS_0 ... PCI_CARDBUS_CIS - 1] = 0xff,
PCI_BASE_ADDRESS_0  158 drivers/gpu/drm/i915/gvt/cfg_space.c 	val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_0];
PCI_BASE_ADDRESS_0  160 drivers/gpu/drm/i915/gvt/cfg_space.c 		start = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_0);
PCI_BASE_ADDRESS_0  162 drivers/gpu/drm/i915/gvt/cfg_space.c 		start = *(u32 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_0);
PCI_BASE_ADDRESS_0  240 drivers/gpu/drm/i915/gvt/cfg_space.c 		case PCI_BASE_ADDRESS_0:
PCI_BASE_ADDRESS_0  264 drivers/gpu/drm/i915/gvt/cfg_space.c 		case PCI_BASE_ADDRESS_0:
PCI_BASE_ADDRESS_0  321 drivers/gpu/drm/i915/gvt/cfg_space.c 	case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_5:
PCI_BASE_ADDRESS_0  956 drivers/gpu/drm/i915/gvt/kvmgt.c 		ret = intel_vgpu_bar_rw(vgpu, PCI_BASE_ADDRESS_0, pos,
PCI_BASE_ADDRESS_0  989 drivers/gpu/drm/i915/gvt/kvmgt.c 	if (index != PCI_BASE_ADDRESS_0)
PCI_BASE_ADDRESS_0  993 drivers/gpu/drm/i915/gvt/kvmgt.c 		intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0);
PCI_BASE_ADDRESS_0   49 drivers/gpu/drm/i915/gvt/mmio.c 	u64 gttmmio_gpa = intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0);
PCI_BASE_ADDRESS_0  346 drivers/infiniband/hw/hfi1/pcie.c 	ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
PCI_BASE_ADDRESS_0  397 drivers/infiniband/hw/hfi1/pcie.c 	ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
PCI_BASE_ADDRESS_0  369 drivers/infiniband/hw/qib/qib_pcie.c 	r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
PCI_BASE_ADDRESS_0 1131 drivers/mfd/lpc_ich.c 		pci_bus_read_config_dword(bus, spi, PCI_BASE_ADDRESS_0,
PCI_BASE_ADDRESS_0  172 drivers/misc/cxl/pci.c 	pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val);
PCI_BASE_ADDRESS_0  409 drivers/mtd/devices/pmc551.c 	pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &cfg);
PCI_BASE_ADDRESS_0  411 drivers/mtd/devices/pmc551.c 	pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, ~0);
PCI_BASE_ADDRESS_0  412 drivers/mtd/devices/pmc551.c 	pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &size);
PCI_BASE_ADDRESS_0  415 drivers/mtd/devices/pmc551.c 	pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, cfg);
PCI_BASE_ADDRESS_0 1314 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c 	pci_read_config_dword(oct->pci_dev, PCI_BASE_ADDRESS_0, &data32);
PCI_BASE_ADDRESS_0  804 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c 	return t4_get_window(adap, PCI_BASE_ADDRESS_0,
PCI_BASE_ADDRESS_0  350 drivers/net/wan/pc300too.c 	pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, scaphys);
PCI_BASE_ADDRESS_0  352 drivers/net/wan/pc300too.c 	pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, plxphys);
PCI_BASE_ADDRESS_0   64 drivers/net/wireless/ath/ath9k/ath9k_pci_owl_loader.c 	pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &bar0);
PCI_BASE_ADDRESS_0   65 drivers/net/wireless/ath/ath9k/ath9k_pci_owl_loader.c 	pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0,
PCI_BASE_ADDRESS_0   95 drivers/net/wireless/ath/ath9k/ath9k_pci_owl_loader.c 	pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, bar0);
PCI_BASE_ADDRESS_0  682 drivers/net/wireless/intersil/p54/p54usb.c 	P54U_WRITE(NET2280_BRG_CFG_U32, PCI_BASE_ADDRESS_0,
PCI_BASE_ADDRESS_0  707 drivers/net/wireless/intersil/p54/p54usb.c 	P54U_WRITE(NET2280_DEV_CFG_U32, 0x10000 | PCI_BASE_ADDRESS_0,
PCI_BASE_ADDRESS_0  143 drivers/net/wireless/intersil/prism54/islpci_hotplug.c 	rvalue = pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &mem_addr);
PCI_BASE_ADDRESS_0  209 drivers/of/address.c 		if ((val & 0xff) == ((bar_no * 4) + PCI_BASE_ADDRESS_0)) {
PCI_BASE_ADDRESS_0  409 drivers/pci/controller/dwc/pci-keystone.c 	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
PCI_BASE_ADDRESS_0  481 drivers/pci/controller/dwc/pci-keystone.c 	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1);
PCI_BASE_ADDRESS_0  482 drivers/pci/controller/dwc/pci-keystone.c 	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);
PCI_BASE_ADDRESS_0  490 drivers/pci/controller/dwc/pci-keystone.c 	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
PCI_BASE_ADDRESS_0  926 drivers/pci/controller/dwc/pci-keystone.c 	dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, APP_ADDR_SPACE_0 - 1);
PCI_BASE_ADDRESS_0  927 drivers/pci/controller/dwc/pci-keystone.c 	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, flags);
PCI_BASE_ADDRESS_0   27 drivers/pci/controller/dwc/pcie-designware-ep.c 	reg = PCI_BASE_ADDRESS_0 + (4 * bar);
PCI_BASE_ADDRESS_0  140 drivers/pci/controller/dwc/pcie-designware-ep.c 	u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
PCI_BASE_ADDRESS_0  426 drivers/pci/controller/dwc/pcie-designware-ep.c 	reg = PCI_BASE_ADDRESS_0 + (4 * bir);
PCI_BASE_ADDRESS_0  672 drivers/pci/controller/dwc/pcie-designware-host.c 	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
PCI_BASE_ADDRESS_0  709 drivers/pci/controller/dwc/pcie-designware-host.c 	dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
PCI_BASE_ADDRESS_0  745 drivers/pci/controller/dwc/pcie-tegra194.c 	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
PCI_BASE_ADDRESS_0 1706 drivers/pci/controller/pci-hyperv.c 						PCI_BASE_ADDRESS_0 + (4 * i),
PCI_BASE_ADDRESS_0 1711 drivers/pci/controller/pci-hyperv.c 						PCI_BASE_ADDRESS_0 + (4 * i),
PCI_BASE_ADDRESS_0 1718 drivers/pci/controller/pci-hyperv.c 						PCI_BASE_ADDRESS_0 + (4 * i),
PCI_BASE_ADDRESS_0  263 drivers/pci/controller/pci-rcar-gen2.c 	iowrite32(val, reg + PCI_BASE_ADDRESS_0);
PCI_BASE_ADDRESS_0  180 drivers/pci/controller/pci-versatile.c 	writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_0);
PCI_BASE_ADDRESS_0  147 drivers/pci/controller/pci-xgene.c 	if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) ||
PCI_BASE_ADDRESS_0  515 drivers/pci/controller/pci-xgene.c 		bar_addr = cfg_base + PCI_BASE_ADDRESS_0;
PCI_BASE_ADDRESS_0  164 drivers/pci/controller/pcie-altera.c 	    (offset == PCI_BASE_ADDRESS_0))
PCI_BASE_ADDRESS_0  338 drivers/pci/controller/pcie-tango.c 	pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0x80000000);
PCI_BASE_ADDRESS_0  334 drivers/pci/hotplug/ibmphp_pci.c 		PCI_BASE_ADDRESS_0,
PCI_BASE_ADDRESS_0  569 drivers/pci/hotplug/ibmphp_pci.c 		PCI_BASE_ADDRESS_0,
PCI_BASE_ADDRESS_0 1058 drivers/pci/hotplug/ibmphp_pci.c 		PCI_BASE_ADDRESS_0,
PCI_BASE_ADDRESS_0 1187 drivers/pci/hotplug/ibmphp_pci.c 		PCI_BASE_ADDRESS_0,
PCI_BASE_ADDRESS_0 1315 drivers/pci/hotplug/ibmphp_pci.c 		PCI_BASE_ADDRESS_0,
PCI_BASE_ADDRESS_0   84 drivers/pci/pci-bridge-emul.c 	[PCI_BASE_ADDRESS_0 / 4] = { .ro = ~0 },
PCI_BASE_ADDRESS_0  333 drivers/pci/probe.c 		reg = PCI_BASE_ADDRESS_0 + (pos << 2);
PCI_BASE_ADDRESS_0  515 drivers/pci/quirks.c 	pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), &region);
PCI_BASE_ADDRESS_0  532 drivers/pci/quirks.c 		 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
PCI_BASE_ADDRESS_0   70 drivers/pci/setup-res.c 		reg = PCI_BASE_ADDRESS_0 + 4 * resno;
PCI_BASE_ADDRESS_0 1039 drivers/pcmcia/yenta_socket.c 	config_writel(socket, PCI_BASE_ADDRESS_0, region.start);
PCI_BASE_ADDRESS_0  555 drivers/scsi/gdth.c 		pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, i);
PCI_BASE_ADDRESS_0  786 drivers/scsi/gdth.c 		pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, i);
PCI_BASE_ADDRESS_0 7401 drivers/scsi/hpsa.c 	if (pci_bar_addr == PCI_BASE_ADDRESS_0)	/* looking for BAR zero? */
PCI_BASE_ADDRESS_0 7426 drivers/scsi/hpsa.c 		if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
PCI_BASE_ADDRESS_0 1350 drivers/scsi/lpfc/lpfc_mbox.c 	pci_read_config_dword(phba->pcidev, PCI_BASE_ADDRESS_0, &bar_low);
PCI_BASE_ADDRESS_0  199 drivers/ssb/driver_gige.c 	gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_0, base);
PCI_BASE_ADDRESS_0  861 drivers/usb/early/ehci-dbgp.c 	if (bar != PCI_BASE_ADDRESS_0) {
PCI_BASE_ADDRESS_0  867 drivers/usb/early/ehci-dbgp.c 	bar_val = read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0);
PCI_BASE_ADDRESS_0   45 drivers/usb/early/xhci-dbc.c 	val = read_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0);
PCI_BASE_ADDRESS_0   46 drivers/usb/early/xhci-dbc.c 	write_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0, ~0);
PCI_BASE_ADDRESS_0   47 drivers/usb/early/xhci-dbc.c 	sz = read_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0);
PCI_BASE_ADDRESS_0   48 drivers/usb/early/xhci-dbc.c 	write_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0, val);
PCI_BASE_ADDRESS_0   60 drivers/usb/early/xhci-dbc.c 		val = read_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0 + 4);
PCI_BASE_ADDRESS_0   61 drivers/usb/early/xhci-dbc.c 		write_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0 + 4, ~0);
PCI_BASE_ADDRESS_0   62 drivers/usb/early/xhci-dbc.c 		sz = read_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0 + 4);
PCI_BASE_ADDRESS_0   63 drivers/usb/early/xhci-dbc.c 		write_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0 + 4, val);
PCI_BASE_ADDRESS_0   35 drivers/vfio/pci/vfio_pci_config.c 	((offset >= PCI_BASE_ADDRESS_0 && offset < PCI_BASE_ADDRESS_5 + 4) || \
PCI_BASE_ADDRESS_0  414 drivers/vfio/pci/vfio_pci_config.c 	for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4, rbar++)
PCI_BASE_ADDRESS_0  456 drivers/vfio/pci/vfio_pci_config.c 	bar = (__le32 *)&vdev->vconfig[PCI_BASE_ADDRESS_0];
PCI_BASE_ADDRESS_0  522 drivers/vfio/pci/vfio_pci_config.c 	int i = 0, pos = PCI_BASE_ADDRESS_0, ret;
PCI_BASE_ADDRESS_0  644 drivers/vfio/pci/vfio_pci_config.c 	p_setd(perm, PCI_BASE_ADDRESS_0, ALL_VIRT, ALL_WRITE);
PCI_BASE_ADDRESS_0 1671 drivers/vfio/pci/vfio_pci_config.c 	vdev->rbar[0] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_0]);
PCI_BASE_ADDRESS_0  449 drivers/video/console/sticore.c 			    (offs < PCI_BASE_ADDRESS_0 ||
PCI_BASE_ADDRESS_0  456 drivers/video/console/sticore.c 			newhpa = pci_resource_start (sti->pd, (offs - PCI_BASE_ADDRESS_0) / 4);
PCI_BASE_ADDRESS_0 2945 drivers/video/fbdev/aty/atyfb_base.c 		int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
PCI_BASE_ADDRESS_0 1682 drivers/video/fbdev/matrox/matroxfb_base.c 		minfo->devflags.fbResource = PCI_BASE_ADDRESS_0;
PCI_BASE_ADDRESS_0  289 drivers/video/fbdev/sunxvr500.c 	pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0,
PCI_BASE_ADDRESS_0  173 drivers/xen/xen-pciback/conf_space_header.c 	unsigned int pos = (offset - PCI_BASE_ADDRESS_0) / 4;
PCI_BASE_ADDRESS_0  234 drivers/xen/xen-pciback/conf_space_header.c 		pos = (offset - PCI_BASE_ADDRESS_0) / 4;
PCI_BASE_ADDRESS_0  381 drivers/xen/xen-pciback/conf_space_header.c 	CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
PCI_BASE_ADDRESS_0  392 drivers/xen/xen-pciback/conf_space_header.c 	CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
PCI_BASE_ADDRESS_0  235 samples/vfio-mdev/mbochs.c 	STORE_LE32((u32 *) &mdev_state->vconfig[PCI_BASE_ADDRESS_0],
PCI_BASE_ADDRESS_0  309 samples/vfio-mdev/mbochs.c 	int index = (offset - PCI_BASE_ADDRESS_0) / 0x04;
PCI_BASE_ADDRESS_0  313 samples/vfio-mdev/mbochs.c 	case PCI_BASE_ADDRESS_0:
PCI_BASE_ADDRESS_0  131 samples/vfio-mdev/mdpy.c 	STORE_LE32((u32 *) &mdev_state->vconfig[PCI_BASE_ADDRESS_0],
PCI_BASE_ADDRESS_0  157 samples/vfio-mdev/mdpy.c 	case PCI_BASE_ADDRESS_0:
PCI_BASE_ADDRESS_0  603 samples/vfio-mdev/mtty.c 	pos = PCI_BASE_ADDRESS_0;
PCI_BASE_ADDRESS_0 1837 sound/pci/ctxfi/cthw20k1.c 	pci_read_config_dword(pci, PCI_BASE_ADDRESS_0, &bar0);
PCI_BASE_ADDRESS_0 1853 sound/pci/ctxfi/cthw20k1.c 	pci_write_config_dword(pci, PCI_BASE_ADDRESS_0, bar5);