PCIE_LC_LINK_WIDTH_CNTL 1281 drivers/gpu/drm/amd/amdgpu/si.c 	link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
PCIE_LC_LINK_WIDTH_CNTL 1330 drivers/gpu/drm/amd/amdgpu/si.c 	link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
PCIE_LC_LINK_WIDTH_CNTL 1336 drivers/gpu/drm/amd/amdgpu/si.c 	WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
PCIE_LC_LINK_WIDTH_CNTL 1699 drivers/gpu/drm/amd/amdgpu/si.c 				tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
PCIE_LC_LINK_WIDTH_CNTL 1704 drivers/gpu/drm/amd/amdgpu/si.c 					WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
PCIE_LC_LINK_WIDTH_CNTL 1932 drivers/gpu/drm/amd/amdgpu/si.c 			orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
PCIE_LC_LINK_WIDTH_CNTL 1936 drivers/gpu/drm/amd/amdgpu/si.c 				WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
PCIE_LC_LINK_WIDTH_CNTL  164 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
PCIE_LC_LINK_WIDTH_CNTL 4827 drivers/gpu/drm/radeon/ci_dpm.c 	link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK;
PCIE_LC_LINK_WIDTH_CNTL 9578 drivers/gpu/drm/radeon/cik.c 				tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
PCIE_LC_LINK_WIDTH_CNTL 9583 drivers/gpu/drm/radeon/cik.c 					WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
PCIE_LC_LINK_WIDTH_CNTL 9736 drivers/gpu/drm/radeon/cik.c 			orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
PCIE_LC_LINK_WIDTH_CNTL 9740 drivers/gpu/drm/radeon/cik.c 				WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
PCIE_LC_LINK_WIDTH_CNTL 5357 drivers/gpu/drm/radeon/evergreen.c 		link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
PCIE_LC_LINK_WIDTH_CNTL 5359 drivers/gpu/drm/radeon/evergreen.c 		WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
PCIE_LC_LINK_WIDTH_CNTL 5378 drivers/gpu/drm/radeon/evergreen.c 		link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
PCIE_LC_LINK_WIDTH_CNTL 5384 drivers/gpu/drm/radeon/evergreen.c 		WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
PCIE_LC_LINK_WIDTH_CNTL 5508 drivers/gpu/drm/radeon/evergreen.c 			data = orig = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
PCIE_LC_LINK_WIDTH_CNTL 5512 drivers/gpu/drm/radeon/evergreen.c 				WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
PCIE_LC_LINK_WIDTH_CNTL 4530 drivers/gpu/drm/radeon/r600.c 		link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
PCIE_LC_LINK_WIDTH_CNTL 4532 drivers/gpu/drm/radeon/r600.c 		WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
PCIE_LC_LINK_WIDTH_CNTL 4533 drivers/gpu/drm/radeon/r600.c 		link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
PCIE_LC_LINK_WIDTH_CNTL 4539 drivers/gpu/drm/radeon/r600.c 			WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
PCIE_LC_LINK_WIDTH_CNTL 4542 drivers/gpu/drm/radeon/r600.c 			WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
PCIE_LC_LINK_WIDTH_CNTL 4595 drivers/gpu/drm/radeon/r600.c 		link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
PCIE_LC_LINK_WIDTH_CNTL 4601 drivers/gpu/drm/radeon/r600.c 		WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
PCIE_LC_LINK_WIDTH_CNTL 2050 drivers/gpu/drm/radeon/rv770.c 	link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
PCIE_LC_LINK_WIDTH_CNTL 2052 drivers/gpu/drm/radeon/rv770.c 	WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
PCIE_LC_LINK_WIDTH_CNTL 2053 drivers/gpu/drm/radeon/rv770.c 	link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
PCIE_LC_LINK_WIDTH_CNTL 2060 drivers/gpu/drm/radeon/rv770.c 		WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
PCIE_LC_LINK_WIDTH_CNTL 2063 drivers/gpu/drm/radeon/rv770.c 		WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
PCIE_LC_LINK_WIDTH_CNTL 2096 drivers/gpu/drm/radeon/rv770.c 		link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
PCIE_LC_LINK_WIDTH_CNTL 2102 drivers/gpu/drm/radeon/rv770.c 		WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
PCIE_LC_LINK_WIDTH_CNTL 7161 drivers/gpu/drm/radeon/si.c 				tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
PCIE_LC_LINK_WIDTH_CNTL 7166 drivers/gpu/drm/radeon/si.c 					WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
PCIE_LC_LINK_WIDTH_CNTL 7356 drivers/gpu/drm/radeon/si.c 			orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
PCIE_LC_LINK_WIDTH_CNTL 7360 drivers/gpu/drm/radeon/si.c 				WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);