PA_FPGA 39 arch/sh/include/mach-common/mach/sdk7780.h #define FPGA_SRSTR (PA_FPGA + 0x000) /* System reset */ PA_FPGA 40 arch/sh/include/mach-common/mach/sdk7780.h #define FPGA_IRQ0SR (PA_FPGA + 0x010) /* IRQ0 status */ PA_FPGA 41 arch/sh/include/mach-common/mach/sdk7780.h #define FPGA_IRQ0MR (PA_FPGA + 0x020) /* IRQ0 mask */ PA_FPGA 42 arch/sh/include/mach-common/mach/sdk7780.h #define FPGA_BDMR (PA_FPGA + 0x030) /* Board operating mode */ PA_FPGA 43 arch/sh/include/mach-common/mach/sdk7780.h #define FPGA_INTT0PRTR (PA_FPGA + 0x040) /* Interrupt test mode0 port */ PA_FPGA 44 arch/sh/include/mach-common/mach/sdk7780.h #define FPGA_INTT0SELR (PA_FPGA + 0x050) /* Int. test mode0 select */ PA_FPGA 45 arch/sh/include/mach-common/mach/sdk7780.h #define FPGA_INTT1POLR (PA_FPGA + 0x060) /* Int. test mode0 polarity */ PA_FPGA 46 arch/sh/include/mach-common/mach/sdk7780.h #define FPGA_NMIR (PA_FPGA + 0x070) /* NMI source */ PA_FPGA 47 arch/sh/include/mach-common/mach/sdk7780.h #define FPGA_NMIMR (PA_FPGA + 0x080) /* NMI mask */ PA_FPGA 48 arch/sh/include/mach-common/mach/sdk7780.h #define FPGA_IRQR (PA_FPGA + 0x090) /* IRQX source */ PA_FPGA 49 arch/sh/include/mach-common/mach/sdk7780.h #define FPGA_IRQMR (PA_FPGA + 0x0A0) /* IRQX mask */ PA_FPGA 50 arch/sh/include/mach-common/mach/sdk7780.h #define FPGA_SLEDR (PA_FPGA + 0x0B0) /* LED control */ PA_FPGA 52 arch/sh/include/mach-common/mach/sdk7780.h #define FPGA_MAPSWR (PA_FPGA + 0x0C0) /* Map switch */ PA_FPGA 53 arch/sh/include/mach-common/mach/sdk7780.h #define FPGA_FPVERR (PA_FPGA + 0x0D0) /* FPGA version */ PA_FPGA 54 arch/sh/include/mach-common/mach/sdk7780.h #define FPGA_FPDATER (PA_FPGA + 0x0E0) /* FPGA date */ PA_FPGA 55 arch/sh/include/mach-common/mach/sdk7780.h #define FPGA_RSE (PA_FPGA + 0x100) /* Reset source */ PA_FPGA 56 arch/sh/include/mach-common/mach/sdk7780.h #define FPGA_EASR (PA_FPGA + 0x110) /* External area select */ PA_FPGA 57 arch/sh/include/mach-common/mach/sdk7780.h #define FPGA_SPER (PA_FPGA + 0x120) /* Serial port enable */ PA_FPGA 58 arch/sh/include/mach-common/mach/sdk7780.h #define FPGA_IMSR (PA_FPGA + 0x130) /* Interrupt mode select */ PA_FPGA 59 arch/sh/include/mach-common/mach/sdk7780.h #define FPGA_PCIMR (PA_FPGA + 0x140) /* PCI Mode */ PA_FPGA 60 arch/sh/include/mach-common/mach/sdk7780.h #define FPGA_DIPSWMR (PA_FPGA + 0x150) /* DIPSW monitor */ PA_FPGA 61 arch/sh/include/mach-common/mach/sdk7780.h #define FPGA_FPODR (PA_FPGA + 0x160) /* Output port data */ PA_FPGA 62 arch/sh/include/mach-common/mach/sdk7780.h #define FPGA_ATAESR (PA_FPGA + 0x170) /* ATA extended bus status */ PA_FPGA 63 arch/sh/include/mach-common/mach/sdk7780.h #define FPGA_IRQPOLR (PA_FPGA + 0x180) /* IRQx polarity */ PA_FPGA 54 arch/sh/include/mach-se/mach/se7721.h #define FPGA_ILSR1 (PA_FPGA + 0x02) PA_FPGA 55 arch/sh/include/mach-se/mach/se7721.h #define FPGA_ILSR2 (PA_FPGA + 0x03) PA_FPGA 56 arch/sh/include/mach-se/mach/se7721.h #define FPGA_ILSR3 (PA_FPGA + 0x04) PA_FPGA 57 arch/sh/include/mach-se/mach/se7721.h #define FPGA_ILSR4 (PA_FPGA + 0x05) PA_FPGA 58 arch/sh/include/mach-se/mach/se7721.h #define FPGA_ILSR5 (PA_FPGA + 0x06) PA_FPGA 59 arch/sh/include/mach-se/mach/se7721.h #define FPGA_ILSR6 (PA_FPGA + 0x07) PA_FPGA 60 arch/sh/include/mach-se/mach/se7721.h #define FPGA_ILSR7 (PA_FPGA + 0x08) PA_FPGA 61 arch/sh/include/mach-se/mach/se7721.h #define FPGA_ILSR8 (PA_FPGA + 0x09) PA_FPGA 50 arch/sh/include/mach-se/mach/se7780.h #define FPGA_SFTRST (PA_FPGA + 0) /* Soft reset register */ PA_FPGA 51 arch/sh/include/mach-se/mach/se7780.h #define FPGA_INTMSK1 (PA_FPGA + 2) /* Interrupt Mask register 1 */ PA_FPGA 52 arch/sh/include/mach-se/mach/se7780.h #define FPGA_INTMSK2 (PA_FPGA + 4) /* Interrupt Mask register 2 */ PA_FPGA 53 arch/sh/include/mach-se/mach/se7780.h #define FPGA_INTSEL1 (PA_FPGA + 6) /* Interrupt select register 1 */ PA_FPGA 54 arch/sh/include/mach-se/mach/se7780.h #define FPGA_INTSEL2 (PA_FPGA + 8) /* Interrupt select register 2 */ PA_FPGA 55 arch/sh/include/mach-se/mach/se7780.h #define FPGA_INTSEL3 (PA_FPGA + 10) /* Interrupt select register 3 */ PA_FPGA 56 arch/sh/include/mach-se/mach/se7780.h #define FPGA_PCI_INTSEL1 (PA_FPGA + 12) /* PCI Interrupt select register 1 */ PA_FPGA 57 arch/sh/include/mach-se/mach/se7780.h #define FPGA_PCI_INTSEL2 (PA_FPGA + 14) /* PCI Interrupt select register 2 */ PA_FPGA 58 arch/sh/include/mach-se/mach/se7780.h #define FPGA_INTSET (PA_FPGA + 16) /* IRQ/IRL select register */ PA_FPGA 59 arch/sh/include/mach-se/mach/se7780.h #define FPGA_INTSTS1 (PA_FPGA + 18) /* Interrupt status register 1 */ PA_FPGA 60 arch/sh/include/mach-se/mach/se7780.h #define FPGA_INTSTS2 (PA_FPGA + 20) /* Interrupt status register 2 */ PA_FPGA 61 arch/sh/include/mach-se/mach/se7780.h #define FPGA_REQSEL (PA_FPGA + 22) /* REQ/GNT select register */ PA_FPGA 62 arch/sh/include/mach-se/mach/se7780.h #define FPGA_DBG_LED (PA_FPGA + 32) /* Debug LED(D-LED[8:1] */ PA_FPGA 64 arch/sh/include/mach-se/mach/se7780.h #define FPGA_IVDRID (PA_FPGA + 36) /* iVDR ID Register */ PA_FPGA 65 arch/sh/include/mach-se/mach/se7780.h #define FPGA_IVDRPW (PA_FPGA + 38) /* iVDR Power ON Register */ PA_FPGA 66 arch/sh/include/mach-se/mach/se7780.h #define FPGA_MMCID (PA_FPGA + 40) /* MMC ID Register */