PACKET3_SET_CONTEXT_REG_START  942 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 						PACKET3_SET_CONTEXT_REG_START);
PACKET3_SET_CONTEXT_REG_START  952 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
PACKET3_SET_CONTEXT_REG_START 2734 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 						  PACKET3_SET_CONTEXT_REG_START);
PACKET3_SET_CONTEXT_REG_START 2742 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
PACKET3_SET_CONTEXT_REG_START 2067 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 				amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
PACKET3_SET_CONTEXT_REG_START 2911 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 	buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
PACKET3_SET_CONTEXT_REG_START 2562 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 				amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
PACKET3_SET_CONTEXT_REG_START 2570 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
PACKET3_SET_CONTEXT_REG_START 3992 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 				buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
PACKET3_SET_CONTEXT_REG_START 4002 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
PACKET3_SET_CONTEXT_REG_START 1267 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 						PACKET3_SET_CONTEXT_REG_START);
PACKET3_SET_CONTEXT_REG_START 1278 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 			PACKET3_SET_CONTEXT_REG_START);
PACKET3_SET_CONTEXT_REG_START 4229 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 				       ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
PACKET3_SET_CONTEXT_REG_START 4237 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
PACKET3_SET_CONTEXT_REG_START 1472 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 						PACKET3_SET_CONTEXT_REG_START);
PACKET3_SET_CONTEXT_REG_START 3170 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 				       ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
PACKET3_SET_CONTEXT_REG_START 6747 drivers/gpu/drm/radeon/cik.c 	buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
PACKET3_SET_CONTEXT_REG_START 2318 drivers/gpu/drm/radeon/evergreen_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START;
PACKET3_SET_CONTEXT_REG_START 2320 drivers/gpu/drm/radeon/evergreen_cs.c 		if ((start_reg < PACKET3_SET_CONTEXT_REG_START) ||
PACKET3_SET_CONTEXT_REG_START 2629 drivers/gpu/drm/radeon/evergreen_cs.c 		allowed_reg_base -= PACKET3_SET_CONTEXT_REG_START;
PACKET3_SET_CONTEXT_REG_START 3504 drivers/gpu/drm/radeon/evergreen_cs.c 		allowed_reg_base -= PACKET3_SET_CONTEXT_REG_START;
PACKET3_SET_CONTEXT_REG_START 5748 drivers/gpu/drm/radeon/si.c 	buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);