PACKET0 1056 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c data[0] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA0, 0); PACKET0 1057 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c data[1] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA1, 0); PACKET0 1058 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c data[2] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_CMD, 0); PACKET0 1059 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c data[3] = PACKET0(offset[offset_idx] + UVD_NO_OP, 0); PACKET0 391 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); PACKET0 424 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0); PACKET0 426 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0); PACKET0 428 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0); PACKET0 431 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0); PACKET0 722 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.jpeg_pitch, 0)); PACKET0 175 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); PACKET0 179 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); PACKET0 183 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); PACKET0 188 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); PACKET0 191 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); PACKET0 451 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); PACKET0 453 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); PACKET0 455 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); PACKET0 457 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); PACKET0 460 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); PACKET0 462 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); PACKET0 464 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); PACKET0 487 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); PACKET0 516 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0)); PACKET0 518 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); PACKET0 529 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0)); PACKET0 172 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); PACKET0 176 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); PACKET0 180 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); PACKET0 185 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); PACKET0 188 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); PACKET0 468 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); PACKET0 470 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); PACKET0 472 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); PACKET0 474 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); PACKET0 477 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); PACKET0 479 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); PACKET0 481 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); PACKET0 503 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); PACKET0 532 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); PACKET0 534 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0)); PACKET0 536 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); PACKET0 547 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0)); PACKET0 487 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); PACKET0 491 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); PACKET0 495 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); PACKET0 500 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); PACKET0 503 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); PACKET0 901 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); PACKET0 903 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); PACKET0 905 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); PACKET0 907 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); PACKET0 910 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); PACKET0 912 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); PACKET0 914 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); PACKET0 967 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); PACKET0 998 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0)); PACKET0 1001 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); PACKET0 1003 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0)); PACKET0 1005 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); PACKET0 1034 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); PACKET0 1036 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); PACKET0 1038 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); PACKET0 1047 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); PACKET0 1049 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); PACKET0 1051 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0)); PACKET0 1053 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); PACKET0 1062 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); PACKET0 1064 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); PACKET0 1066 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0)); PACKET0 1068 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH9, 0)); PACKET0 1070 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); PACKET0 1081 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0)); PACKET0 550 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, PACKET0 555 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, PACKET0 560 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, PACKET0 566 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, PACKET0 570 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, PACKET0 1163 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); PACKET0 1166 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); PACKET0 1169 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); PACKET0 1172 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); PACKET0 1176 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); PACKET0 1179 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); PACKET0 1182 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); PACKET0 1237 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); PACKET0 1299 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0)); PACKET0 1303 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); PACKET0 1306 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); PACKET0 1309 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0)); PACKET0 1341 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); PACKET0 1344 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); PACKET0 1347 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); PACKET0 1357 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); PACKET0 1360 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); PACKET0 1363 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0)); PACKET0 1366 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); PACKET0 1393 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0)); PACKET0 1446 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); PACKET0 1449 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); PACKET0 1465 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); PACKET0 1485 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0)); PACKET0 1488 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); PACKET0 1491 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); PACKET0 1494 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); PACKET0 1498 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); PACKET0 1501 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); PACKET0 1504 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); PACKET0 1525 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0)); PACKET0 1529 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); PACKET0 1532 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); PACKET0 1535 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0)); PACKET0 1546 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); PACKET0 1549 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); PACKET0 1552 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0)); PACKET0 1555 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); PACKET0 1580 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); PACKET0 1583 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); PACKET0 1586 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); PACKET0 2147 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0)); PACKET0 2266 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c .nop = PACKET0(0x81ff, 0), PACKET0 1494 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); PACKET0 1496 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); PACKET0 1511 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); PACKET0 1530 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0)); PACKET0 1549 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0)); PACKET0 1552 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); PACKET0 1555 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); PACKET0 1558 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); PACKET0 1561 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); PACKET0 1564 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); PACKET0 1567 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); PACKET0 1588 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_vmid, 0)); PACKET0 1591 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_low, 0)); PACKET0 1593 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_high, 0)); PACKET0 1595 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_size, 0)); PACKET0 1604 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); PACKET0 1607 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); PACKET0 1610 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.gp_scratch8, 0)); PACKET0 1613 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); PACKET0 1638 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); PACKET0 1641 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); PACKET0 1644 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); PACKET0 2106 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); PACKET0 2108 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); PACKET0 8188 drivers/gpu/drm/radeon/cik.c r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0)); PACKET0 4987 drivers/gpu/drm/radeon/evergreen.c r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0)); PACKET0 2059 drivers/gpu/drm/radeon/ni.c r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0)); PACKET0 2696 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2), 0)); PACKET0 2700 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0)); PACKET0 2704 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0)); PACKET0 849 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); PACKET0 852 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); PACKET0 865 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); PACKET0 867 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); PACKET0 870 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); PACKET0 874 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); PACKET0 876 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); PACKET0 951 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); PACKET0 953 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); PACKET0 990 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); PACKET0 3670 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, PACKET0(scratch, 0)); PACKET0 3697 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0)); PACKET0 3701 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1)); PACKET0 3725 drivers/gpu/drm/radeon/r100.c ib.ptr[0] = PACKET0(scratch, 0); PACKET0 105 drivers/gpu/drm/radeon/r200.c radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); PACKET0 113 drivers/gpu/drm/radeon/r200.c radeon_ring_write(ring, PACKET0(0x720, 2)); PACKET0 120 drivers/gpu/drm/radeon/r200.c radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); PACKET0 222 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0)); PACKET0 224 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0)); PACKET0 227 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); PACKET0 229 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); PACKET0 232 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); PACKET0 236 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); PACKET0 239 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); PACKET0 242 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); PACKET0 244 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); PACKET0 275 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); PACKET0 281 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0)); PACKET0 283 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); PACKET0 287 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); PACKET0 289 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0)); PACKET0 291 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0)); PACKET0 293 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); PACKET0 295 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); PACKET0 297 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); PACKET0 301 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0)); PACKET0 303 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); PACKET0 305 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); PACKET0 307 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0)); PACKET0 317 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0)); PACKET0 326 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0)); PACKET0 328 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0)); PACKET0 331 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0)); PACKET0 225 drivers/gpu/drm/radeon/r420.c radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); PACKET0 241 drivers/gpu/drm/radeon/r420.c radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); PACKET0 2909 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); PACKET0 3095 drivers/gpu/drm/radeon/r600.c r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0)); PACKET0 751 drivers/gpu/drm/radeon/radeon_uvd.c ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0); PACKET0 753 drivers/gpu/drm/radeon/radeon_uvd.c ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0); PACKET0 755 drivers/gpu/drm/radeon/radeon_uvd.c ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0); PACKET0 758 drivers/gpu/drm/radeon/radeon_uvd.c ib.ptr[i] = PACKET0(UVD_NO_OP, 0); PACKET0 75 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); PACKET0 81 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); PACKET0 83 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); PACKET0 85 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); PACKET0 87 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); PACKET0 89 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); PACKET0 91 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); PACKET0 93 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); PACKET0 95 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); PACKET0 97 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); PACKET0 99 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0)); PACKET0 101 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); PACKET0 103 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); PACKET0 105 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0)); PACKET0 115 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0)); PACKET0 124 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0)); PACKET0 126 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0)); PACKET0 128 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0)); PACKET0 130 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(0x20C8, 0)); PACKET0 1745 drivers/gpu/drm/radeon/rv770.c r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0)); PACKET0 6514 drivers/gpu/drm/radeon/si.c r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0)); PACKET0 87 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); PACKET0 89 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); PACKET0 91 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); PACKET0 94 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); PACKET0 96 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); PACKET0 98 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); PACKET0 186 drivers/gpu/drm/radeon/uvd_v1_0.c tmp = PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); PACKET0 190 drivers/gpu/drm/radeon/uvd_v1_0.c tmp = PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); PACKET0 194 drivers/gpu/drm/radeon/uvd_v1_0.c tmp = PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); PACKET0 199 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATUS, 0)); PACKET0 202 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0)); PACKET0 434 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); PACKET0 486 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, PACKET0(UVD_RBC_IB_BASE, 0)); PACKET0 488 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, PACKET0(UVD_RBC_IB_SIZE, 0)); PACKET0 45 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); PACKET0 47 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); PACKET0 49 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); PACKET0 51 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); PACKET0 54 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); PACKET0 56 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); PACKET0 58 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); PACKET0 79 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0)); PACKET0 82 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0)); PACKET0 85 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0)); PACKET0 46 drivers/gpu/drm/radeon/uvd_v3_1.c radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0)); PACKET0 49 drivers/gpu/drm/radeon/uvd_v3_1.c radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0)); PACKET0 52 drivers/gpu/drm/radeon/uvd_v3_1.c radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));