P4_EVENT_IOQ_ACTIVE_ENTRIES 183 arch/x86/events/intel/p4.c [P4_EVENT_IOQ_ACTIVE_ENTRIES] = { /* shared ESCR */ P4_EVENT_IOQ_ACTIVE_ENTRIES 184 arch/x86/events/intel/p4.c .opcode = P4_OPCODE(P4_EVENT_IOQ_ACTIVE_ENTRIES), P4_EVENT_IOQ_ACTIVE_ENTRIES 187 arch/x86/events/intel/p4.c P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, DEFAULT) | P4_EVENT_IOQ_ACTIVE_ENTRIES 188 arch/x86/events/intel/p4.c P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_READ) | P4_EVENT_IOQ_ACTIVE_ENTRIES 189 arch/x86/events/intel/p4.c P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_WRITE) | P4_EVENT_IOQ_ACTIVE_ENTRIES 190 arch/x86/events/intel/p4.c P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_UC) | P4_EVENT_IOQ_ACTIVE_ENTRIES 191 arch/x86/events/intel/p4.c P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WC) | P4_EVENT_IOQ_ACTIVE_ENTRIES 192 arch/x86/events/intel/p4.c P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WT) | P4_EVENT_IOQ_ACTIVE_ENTRIES 193 arch/x86/events/intel/p4.c P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WP) | P4_EVENT_IOQ_ACTIVE_ENTRIES 194 arch/x86/events/intel/p4.c P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WB) | P4_EVENT_IOQ_ACTIVE_ENTRIES 195 arch/x86/events/intel/p4.c P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, OWN) | P4_EVENT_IOQ_ACTIVE_ENTRIES 196 arch/x86/events/intel/p4.c P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, OTHER) | P4_EVENT_IOQ_ACTIVE_ENTRIES 197 arch/x86/events/intel/p4.c P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, PREFETCH),