P4_EVENT_BSQ_CACHE_REFERENCE  151 arch/x86/events/intel/p4.c 	[P4_EVENT_BSQ_CACHE_REFERENCE] = {
P4_EVENT_BSQ_CACHE_REFERENCE  152 arch/x86/events/intel/p4.c 		.opcode		= P4_OPCODE(P4_EVENT_BSQ_CACHE_REFERENCE),
P4_EVENT_BSQ_CACHE_REFERENCE  155 arch/x86/events/intel/p4.c 			P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITS)	|
P4_EVENT_BSQ_CACHE_REFERENCE  156 arch/x86/events/intel/p4.c 			P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITE)	|
P4_EVENT_BSQ_CACHE_REFERENCE  157 arch/x86/events/intel/p4.c 			P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITM)	|
P4_EVENT_BSQ_CACHE_REFERENCE  158 arch/x86/events/intel/p4.c 			P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITS)	|
P4_EVENT_BSQ_CACHE_REFERENCE  159 arch/x86/events/intel/p4.c 			P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITE)	|
P4_EVENT_BSQ_CACHE_REFERENCE  160 arch/x86/events/intel/p4.c 			P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITM)	|
P4_EVENT_BSQ_CACHE_REFERENCE  161 arch/x86/events/intel/p4.c 			P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_MISS)	|
P4_EVENT_BSQ_CACHE_REFERENCE  162 arch/x86/events/intel/p4.c 			P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_MISS)	|
P4_EVENT_BSQ_CACHE_REFERENCE  163 arch/x86/events/intel/p4.c 			P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, WR_2ndL_MISS),
P4_EVENT_BSQ_CACHE_REFERENCE  669 arch/x86/events/intel/p4.c 	p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_BSQ_CACHE_REFERENCE)		|
P4_EVENT_BSQ_CACHE_REFERENCE  670 arch/x86/events/intel/p4.c 		P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITS)	|
P4_EVENT_BSQ_CACHE_REFERENCE  671 arch/x86/events/intel/p4.c 		P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITE)	|
P4_EVENT_BSQ_CACHE_REFERENCE  672 arch/x86/events/intel/p4.c 		P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITM)	|
P4_EVENT_BSQ_CACHE_REFERENCE  673 arch/x86/events/intel/p4.c 		P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITS)	|
P4_EVENT_BSQ_CACHE_REFERENCE  674 arch/x86/events/intel/p4.c 		P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITE)	|
P4_EVENT_BSQ_CACHE_REFERENCE  675 arch/x86/events/intel/p4.c 		P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITM)),
P4_EVENT_BSQ_CACHE_REFERENCE  679 arch/x86/events/intel/p4.c 	p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_BSQ_CACHE_REFERENCE)		|
P4_EVENT_BSQ_CACHE_REFERENCE  680 arch/x86/events/intel/p4.c 		P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_MISS)	|
P4_EVENT_BSQ_CACHE_REFERENCE  681 arch/x86/events/intel/p4.c 		P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_MISS)	|
P4_EVENT_BSQ_CACHE_REFERENCE  682 arch/x86/events/intel/p4.c 		P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, WR_2ndL_MISS)),