P4_EVENT_BSQ_ALLOCATION  213 arch/x86/events/intel/p4.c 	[P4_EVENT_BSQ_ALLOCATION] = {		/* shared ESCR, broken CCCR1 */
P4_EVENT_BSQ_ALLOCATION  214 arch/x86/events/intel/p4.c 		.opcode		= P4_OPCODE(P4_EVENT_BSQ_ALLOCATION),
P4_EVENT_BSQ_ALLOCATION  217 arch/x86/events/intel/p4.c 			P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE0)		|
P4_EVENT_BSQ_ALLOCATION  218 arch/x86/events/intel/p4.c 			P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE1)		|
P4_EVENT_BSQ_ALLOCATION  219 arch/x86/events/intel/p4.c 			P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_LEN0)		|
P4_EVENT_BSQ_ALLOCATION  220 arch/x86/events/intel/p4.c 			P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_LEN1)		|
P4_EVENT_BSQ_ALLOCATION  221 arch/x86/events/intel/p4.c 			P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_IO_TYPE)		|
P4_EVENT_BSQ_ALLOCATION  222 arch/x86/events/intel/p4.c 			P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_LOCK_TYPE)	|
P4_EVENT_BSQ_ALLOCATION  223 arch/x86/events/intel/p4.c 			P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_CACHE_TYPE)	|
P4_EVENT_BSQ_ALLOCATION  224 arch/x86/events/intel/p4.c 			P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_SPLIT_TYPE)	|
P4_EVENT_BSQ_ALLOCATION  225 arch/x86/events/intel/p4.c 			P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_DEM_TYPE)	|
P4_EVENT_BSQ_ALLOCATION  226 arch/x86/events/intel/p4.c 			P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_ORD_TYPE)	|
P4_EVENT_BSQ_ALLOCATION  227 arch/x86/events/intel/p4.c 			P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE0)		|
P4_EVENT_BSQ_ALLOCATION  228 arch/x86/events/intel/p4.c 			P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE1)		|
P4_EVENT_BSQ_ALLOCATION  229 arch/x86/events/intel/p4.c 			P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE2),