P4SEGADDR          16 arch/sh/drivers/superhyway/ops-sh4-202.c #define PHYS_EMI_CBLOCK		P4SEGADDR(0x1ec00000)
P4SEGADDR          17 arch/sh/drivers/superhyway/ops-sh4-202.c #define PHYS_EMI_DBLOCK		P4SEGADDR(0x08000000)
P4SEGADDR          18 arch/sh/drivers/superhyway/ops-sh4-202.c #define PHYS_FEMI_CBLOCK	P4SEGADDR(0x1f800000)
P4SEGADDR          19 arch/sh/drivers/superhyway/ops-sh4-202.c #define PHYS_FEMI_DBLOCK	P4SEGADDR(0x00000000)
P4SEGADDR          21 arch/sh/drivers/superhyway/ops-sh4-202.c #define PHYS_EPBR_BLOCK		P4SEGADDR(0x1de00000)
P4SEGADDR          22 arch/sh/drivers/superhyway/ops-sh4-202.c #define PHYS_DMAC_BLOCK		P4SEGADDR(0x1fa00000)
P4SEGADDR          23 arch/sh/drivers/superhyway/ops-sh4-202.c #define PHYS_PBR_BLOCK		P4SEGADDR(0x1fc00000)
P4SEGADDR          65 arch/sh/drivers/superhyway/ops-sh4-202.c 		.start	= P4SEGADDR(0x1e7ffff8),
P4SEGADDR          66 arch/sh/drivers/superhyway/ops-sh4-202.c 		.end	= P4SEGADDR(0x1e7ffff8 + (sizeof(u32) * 2) - 1),
P4SEGADDR          96 arch/sh/drivers/superhyway/ops-sh4-202.c 		.start	= P4SEGADDR(0x1ffffff8),
P4SEGADDR          97 arch/sh/drivers/superhyway/ops-sh4-202.c 		.end	= P4SEGADDR(0x1ffffff8 + (sizeof(u32) * 2) - 1),
P4SEGADDR         307 arch/sh/include/asm/io.h 		return (void __iomem *)P4SEGADDR(offset);