Op2 53 arch/arm/include/asm/cp15.h #define __ACCESS_CP15(CRn, Op1, CRm, Op2) \ Op2 54 arch/arm/include/asm/cp15.h "mrc", "mcr", __stringify(p15, Op1, %0, CRn, CRm, Op2), u32 Op2 381 arch/arm/kvm/coproc.c { CRn( 0), CRm( 0), Op1( 0), Op2( 5), is32, Op2 385 arch/arm/kvm/coproc.c { CRn( 0), CRm( 0), Op1( 2), Op2( 0), is32, Op2 389 arch/arm/kvm/coproc.c { CRn( 1), CRm( 0), Op1( 0), Op2( 1), is32, Op2 393 arch/arm/kvm/coproc.c { CRn( 1), CRm( 0), Op1( 0), Op2( 2), is32, Op2 398 arch/arm/kvm/coproc.c { CRn(2), CRm( 0), Op1( 0), Op2( 0), is32, Op2 400 arch/arm/kvm/coproc.c { CRn(2), CRm( 0), Op1( 0), Op2( 1), is32, Op2 402 arch/arm/kvm/coproc.c { CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32, Op2 408 arch/arm/kvm/coproc.c { CRn( 3), CRm( 0), Op1( 0), Op2( 0), is32, Op2 412 arch/arm/kvm/coproc.c { CRn( 5), CRm( 0), Op1( 0), Op2( 0), is32, Op2 414 arch/arm/kvm/coproc.c { CRn( 5), CRm( 0), Op1( 0), Op2( 1), is32, Op2 416 arch/arm/kvm/coproc.c { CRn( 5), CRm( 1), Op1( 0), Op2( 0), is32, Op2 418 arch/arm/kvm/coproc.c { CRn( 5), CRm( 1), Op1( 0), Op2( 1), is32, Op2 422 arch/arm/kvm/coproc.c { CRn( 6), CRm( 0), Op1( 0), Op2( 0), is32, Op2 424 arch/arm/kvm/coproc.c { CRn( 6), CRm( 0), Op1( 0), Op2( 2), is32, Op2 433 arch/arm/kvm/coproc.c { CRn( 7), CRm( 6), Op1( 0), Op2( 2), is32, access_dcsw}, Op2 434 arch/arm/kvm/coproc.c { CRn( 7), CRm(10), Op1( 0), Op2( 2), is32, access_dcsw}, Op2 435 arch/arm/kvm/coproc.c { CRn( 7), CRm(14), Op1( 0), Op2( 2), is32, access_dcsw}, Op2 439 arch/arm/kvm/coproc.c { CRn( 9), CRm( 0), Op1( 1), Op2( 2), is32, Op2 441 arch/arm/kvm/coproc.c { CRn( 9), CRm( 0), Op1( 1), Op2( 3), is32, access_l2ectlr}, Op2 446 arch/arm/kvm/coproc.c { CRn( 9), CRm(12), Op1( 0), Op2( 0), is32, access_pmcr}, Op2 447 arch/arm/kvm/coproc.c { CRn( 9), CRm(12), Op1( 0), Op2( 1), is32, access_pmcntenset}, Op2 448 arch/arm/kvm/coproc.c { CRn( 9), CRm(12), Op1( 0), Op2( 2), is32, access_pmcntenclr}, Op2 449 arch/arm/kvm/coproc.c { CRn( 9), CRm(12), Op1( 0), Op2( 3), is32, access_pmovsr}, Op2 450 arch/arm/kvm/coproc.c { CRn( 9), CRm(12), Op1( 0), Op2( 5), is32, access_pmselr}, Op2 451 arch/arm/kvm/coproc.c { CRn( 9), CRm(12), Op1( 0), Op2( 6), is32, access_pmceid0}, Op2 452 arch/arm/kvm/coproc.c { CRn( 9), CRm(12), Op1( 0), Op2( 7), is32, access_pmceid1}, Op2 453 arch/arm/kvm/coproc.c { CRn( 9), CRm(13), Op1( 0), Op2( 0), is32, access_pmccntr}, Op2 454 arch/arm/kvm/coproc.c { CRn( 9), CRm(13), Op1( 0), Op2( 1), is32, access_pmxevtyper}, Op2 455 arch/arm/kvm/coproc.c { CRn( 9), CRm(13), Op1( 0), Op2( 2), is32, access_pmxevcntr}, Op2 456 arch/arm/kvm/coproc.c { CRn( 9), CRm(14), Op1( 0), Op2( 0), is32, access_pmuserenr}, Op2 457 arch/arm/kvm/coproc.c { CRn( 9), CRm(14), Op1( 0), Op2( 1), is32, access_pmintenset}, Op2 458 arch/arm/kvm/coproc.c { CRn( 9), CRm(14), Op1( 0), Op2( 2), is32, access_pmintenclr}, Op2 461 arch/arm/kvm/coproc.c { CRn(10), CRm( 2), Op1( 0), Op2( 0), is32, Op2 463 arch/arm/kvm/coproc.c { CRn(10), CRm( 2), Op1( 0), Op2( 1), is32, Op2 467 arch/arm/kvm/coproc.c { CRn(10), CRm( 3), Op1( 0), Op2( 0), is32, Op2 469 arch/arm/kvm/coproc.c { CRn(10), CRm( 3), Op1( 0), Op2( 1), is32, Op2 476 arch/arm/kvm/coproc.c { CRn(12), CRm( 0), Op1( 0), Op2( 0), is32, Op2 484 arch/arm/kvm/coproc.c { CRn(12), CRm(12), Op1( 0), Op2(5), is32, access_gic_sre }, Op2 487 arch/arm/kvm/coproc.c { CRn(13), CRm( 0), Op1( 0), Op2( 1), is32, Op2 489 arch/arm/kvm/coproc.c { CRn(13), CRm( 0), Op1( 0), Op2( 2), is32, Op2 491 arch/arm/kvm/coproc.c { CRn(13), CRm( 0), Op1( 0), Op2( 3), is32, Op2 493 arch/arm/kvm/coproc.c { CRn(13), CRm( 0), Op1( 0), Op2( 4), is32, Op2 500 arch/arm/kvm/coproc.c { CRn(14), CRm( 1), Op1( 0), Op2( 0), is32, Op2 504 arch/arm/kvm/coproc.c { CRn(14), CRm( 2), Op1( 0), Op2( 0), is32, access_cntp_tval }, Op2 505 arch/arm/kvm/coproc.c { CRn(14), CRm( 2), Op1( 0), Op2( 1), is32, access_cntp_ctl }, Op2 508 arch/arm/kvm/coproc.c { CRn(15), CRm( 0), Op1( 4), Op2( 0), is32, access_cbar}, Op2 550 arch/arm/kvm/coproc.c val |= (x)->Op2 << 1; \ Op2 579 arch/arm/kvm/coproc.c params->CRm, params->Op2, params->is_write); Op2 617 arch/arm/kvm/coproc.c params.Op2 = 0; Op2 683 arch/arm/kvm/coproc.c params.Op2 = (kvm_vcpu_get_hsr(vcpu) >> 17) & 0x7; Op2 741 arch/arm/kvm/coproc.c params->Op2 = ((id & KVM_REG_ARM_32_OPC2_MASK) Op2 757 arch/arm/kvm/coproc.c params->Op2 = 0; Op2 837 arch/arm/kvm/coproc.c { CRn( 0), CRm( 0), Op1( 0), Op2( 0), is32, NULL, get_MIDR }, Op2 838 arch/arm/kvm/coproc.c { CRn( 0), CRm( 0), Op1( 0), Op2( 1), is32, NULL, get_CTR }, Op2 839 arch/arm/kvm/coproc.c { CRn( 0), CRm( 0), Op1( 0), Op2( 2), is32, NULL, get_TCMTR }, Op2 840 arch/arm/kvm/coproc.c { CRn( 0), CRm( 0), Op1( 0), Op2( 3), is32, NULL, get_TLBTR }, Op2 841 arch/arm/kvm/coproc.c { CRn( 0), CRm( 0), Op1( 0), Op2( 6), is32, NULL, get_REVIDR }, Op2 843 arch/arm/kvm/coproc.c { CRn( 0), CRm( 0), Op1( 1), Op2( 1), is32, NULL, get_CLIDR }, Op2 844 arch/arm/kvm/coproc.c { CRn( 0), CRm( 0), Op1( 1), Op2( 7), is32, NULL, get_AIDR }, Op2 846 arch/arm/kvm/coproc.c { CRn( 0), CRm( 1), Op1( 0), Op2( 0), is32, NULL, get_ID_PFR0 }, Op2 847 arch/arm/kvm/coproc.c { CRn( 0), CRm( 1), Op1( 0), Op2( 1), is32, NULL, get_ID_PFR1 }, Op2 848 arch/arm/kvm/coproc.c { CRn( 0), CRm( 1), Op1( 0), Op2( 2), is32, NULL, get_ID_DFR0 }, Op2 849 arch/arm/kvm/coproc.c { CRn( 0), CRm( 1), Op1( 0), Op2( 3), is32, NULL, get_ID_AFR0 }, Op2 850 arch/arm/kvm/coproc.c { CRn( 0), CRm( 1), Op1( 0), Op2( 4), is32, NULL, get_ID_MMFR0 }, Op2 851 arch/arm/kvm/coproc.c { CRn( 0), CRm( 1), Op1( 0), Op2( 5), is32, NULL, get_ID_MMFR1 }, Op2 852 arch/arm/kvm/coproc.c { CRn( 0), CRm( 1), Op1( 0), Op2( 6), is32, NULL, get_ID_MMFR2 }, Op2 853 arch/arm/kvm/coproc.c { CRn( 0), CRm( 1), Op1( 0), Op2( 7), is32, NULL, get_ID_MMFR3 }, Op2 855 arch/arm/kvm/coproc.c { CRn( 0), CRm( 2), Op1( 0), Op2( 0), is32, NULL, get_ID_ISAR0 }, Op2 856 arch/arm/kvm/coproc.c { CRn( 0), CRm( 2), Op1( 0), Op2( 1), is32, NULL, get_ID_ISAR1 }, Op2 857 arch/arm/kvm/coproc.c { CRn( 0), CRm( 2), Op1( 0), Op2( 2), is32, NULL, get_ID_ISAR2 }, Op2 858 arch/arm/kvm/coproc.c { CRn( 0), CRm( 2), Op1( 0), Op2( 3), is32, NULL, get_ID_ISAR3 }, Op2 859 arch/arm/kvm/coproc.c { CRn( 0), CRm( 2), Op1( 0), Op2( 4), is32, NULL, get_ID_ISAR4 }, Op2 860 arch/arm/kvm/coproc.c { CRn( 0), CRm( 2), Op1( 0), Op2( 5), is32, NULL, get_ID_ISAR5 }, Op2 1308 arch/arm/kvm/coproc.c val |= (reg->Op2 << KVM_REG_ARM_32_OPC2_SHIFT); Op2 14 arch/arm/kvm/coproc.h unsigned long Op2; Op2 26 arch/arm/kvm/coproc.h unsigned long Op2; Op2 54 arch/arm/kvm/coproc.h p->CRn, p->CRm, p->Op1, p->Op2, Op2 112 arch/arm/kvm/coproc.h if (i1->Op2 != i2->Op2) Op2 113 arch/arm/kvm/coproc.h return i1->Op2 - i2->Op2; Op2 122 arch/arm/kvm/coproc.h #define Op2(_x) .Op2 = _x Op2 24 arch/arm/kvm/coproc_a15.c { CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32, Op2 27 arch/arm/kvm/coproc_a7.c { CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32, Op2 13 arch/arm/kvm/trace.h unsigned long CRm, unsigned long Op2, bool is_write), Op2 14 arch/arm/kvm/trace.h TP_ARGS(Op1, Rt1, CRn, CRm, Op2, is_write), Op2 21 arch/arm/kvm/trace.h __field( unsigned int, Op2 ) Op2 31 arch/arm/kvm/trace.h __entry->Op2 = Op2; Op2 37 arch/arm/kvm/trace.h __entry->CRm, __entry->Op2) Op2 268 arch/arm64/kvm/sys_regs.c switch (p->Op2) { Op2 318 arch/arm64/kvm/sys_regs.c (u32)r->CRn, (u32)r->CRm, (u32)r->Op2); Op2 734 arch/arm64/kvm/sys_regs.c if (!(p->Op2 & 1)) Op2 768 arch/arm64/kvm/sys_regs.c if (r->Op2 == 2) { Op2 775 arch/arm64/kvm/sys_regs.c } else if (r->Op2 == 0) { Op2 795 arch/arm64/kvm/sys_regs.c idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); Op2 826 arch/arm64/kvm/sys_regs.c if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { Op2 831 arch/arm64/kvm/sys_regs.c idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); Op2 869 arch/arm64/kvm/sys_regs.c if (r->Op2 & 0x1) { Op2 902 arch/arm64/kvm/sys_regs.c if (r->Op2 & 0x1) Op2 983 arch/arm64/kvm/sys_regs.c (u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2); Op2 1078 arch/arm64/kvm/sys_regs.c (u32)r->CRn, (u32)r->CRm, (u32)r->Op2); Op2 1338 arch/arm64/kvm/sys_regs.c Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ Op2 1722 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \ Op2 1724 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \ Op2 1726 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \ Op2 1728 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n } Op2 1731 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n } Op2 1740 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr }, Op2 1742 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, Op2 1746 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, Op2 1749 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 }, Op2 1751 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 }, Op2 1754 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, Op2 1756 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, Op2 1761 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, Op2 1763 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, Op2 1766 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 }, Op2 1778 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, Op2 1782 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi }, Op2 1785 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 }, Op2 1789 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, Op2 1792 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, Op2 1806 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, Op2 1809 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, Op2 1811 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, Op2 1813 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, Op2 1815 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, Op2 1817 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, Op2 1819 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, Op2 1835 arch/arm64/kvm/sys_regs.c CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \ Op2 1842 arch/arm64/kvm/sys_regs.c CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \ Op2 1851 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, Op2 1852 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR }, Op2 1853 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 }, Op2 1854 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 }, Op2 1855 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR }, Op2 1856 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR }, Op2 1857 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR }, Op2 1858 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR }, Op2 1859 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR }, Op2 1860 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR }, Op2 1861 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR }, Op2 1862 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR }, Op2 1867 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, Op2 1868 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, Op2 1869 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, Op2 1872 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr }, Op2 1873 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten }, Op2 1874 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten }, Op2 1875 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs }, Op2 1876 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc }, Op2 1877 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr }, Op2 1878 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid }, Op2 1879 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid }, Op2 1880 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr }, Op2 1881 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper }, Op2 1882 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr }, Op2 1883 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr }, Op2 1884 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten }, Op2 1885 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten }, Op2 1886 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs }, Op2 1888 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR }, Op2 1889 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR }, Op2 1890 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 }, Op2 1891 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 }, Op2 1894 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre }, Op2 1896 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID }, Op2 1967 arch/arm64/kvm/sys_regs.c { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper }, Op2 1969 arch/arm64/kvm/sys_regs.c { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, Op2 1970 arch/arm64/kvm/sys_regs.c { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, Op2 1971 arch/arm64/kvm/sys_regs.c { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, c0_CSSELR }, Op2 1975 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 }, Op2 1976 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr }, Op2 1977 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ Op2 1978 arch/arm64/kvm/sys_regs.c { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 }, Op2 1979 arch/arm64/kvm/sys_regs.c { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ Op2 1980 arch/arm64/kvm/sys_regs.c { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ Op2 2136 arch/arm64/kvm/sys_regs.c params.Op2 = 0; Op2 2193 arch/arm64/kvm/sys_regs.c params.Op2 = (hsr >> 17) & 0x7; Op2 2302 arch/arm64/kvm/sys_regs.c params.Op2 = (esr >> 17) & 0x7; Op2 2338 arch/arm64/kvm/sys_regs.c params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) Op2 2635 arch/arm64/kvm/sys_regs.c (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); Op2 19 arch/arm64/kvm/sys_regs.h u8 Op2; Op2 35 arch/arm64/kvm/sys_regs.h u8 Op2; Op2 69 arch/arm64/kvm/sys_regs.h p->Op0, p->Op1, p->CRn, p->CRm, p->Op2, p->is_write ? "write" : "read"); Op2 135 arch/arm64/kvm/sys_regs.h return i1->Op2 - i2->Op2; Op2 147 arch/arm64/kvm/sys_regs.h #define Op2(_x) .Op2 = _x Op2 153 arch/arm64/kvm/sys_regs.h Op2(sys_reg_Op2(reg)) Op2 49 arch/arm64/kvm/sys_regs_generic_v8.c { Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b001), Op2 168 arch/arm64/kvm/trace.h __field(u8, Op2) Op2 180 arch/arm64/kvm/trace.h __entry->Op2 = reg->Op2; Op2 186 arch/arm64/kvm/trace.h __entry->CRm, __entry->Op2, Op2 203 arch/arm64/kvm/vgic-sys-reg-v3.c u8 idx = r->Op2 & 3;