Op1 53 arch/arm/include/asm/cp15.h #define __ACCESS_CP15(CRn, Op1, CRm, Op2) \ Op1 54 arch/arm/include/asm/cp15.h "mrc", "mcr", __stringify(p15, Op1, %0, CRn, CRm, Op2), u32 Op1 55 arch/arm/include/asm/cp15.h #define __ACCESS_CP15_64(Op1, CRm) \ Op1 56 arch/arm/include/asm/cp15.h "mrrc", "mcrr", __stringify(p15, Op1, %Q0, %R0, CRm), u64 Op1 252 arch/arm/kvm/coproc.c switch (p->Op1) { Op1 381 arch/arm/kvm/coproc.c { CRn( 0), CRm( 0), Op1( 0), Op2( 5), is32, Op1 385 arch/arm/kvm/coproc.c { CRn( 0), CRm( 0), Op1( 2), Op2( 0), is32, Op1 389 arch/arm/kvm/coproc.c { CRn( 1), CRm( 0), Op1( 0), Op2( 1), is32, Op1 393 arch/arm/kvm/coproc.c { CRn( 1), CRm( 0), Op1( 0), Op2( 2), is32, Op1 397 arch/arm/kvm/coproc.c { CRm64( 2), Op1( 0), is64, access_vm_reg, reset_unknown64, c2_TTBR0 }, Op1 398 arch/arm/kvm/coproc.c { CRn(2), CRm( 0), Op1( 0), Op2( 0), is32, Op1 400 arch/arm/kvm/coproc.c { CRn(2), CRm( 0), Op1( 0), Op2( 1), is32, Op1 402 arch/arm/kvm/coproc.c { CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32, Op1 404 arch/arm/kvm/coproc.c { CRm64( 2), Op1( 1), is64, access_vm_reg, reset_unknown64, c2_TTBR1 }, Op1 408 arch/arm/kvm/coproc.c { CRn( 3), CRm( 0), Op1( 0), Op2( 0), is32, Op1 412 arch/arm/kvm/coproc.c { CRn( 5), CRm( 0), Op1( 0), Op2( 0), is32, Op1 414 arch/arm/kvm/coproc.c { CRn( 5), CRm( 0), Op1( 0), Op2( 1), is32, Op1 416 arch/arm/kvm/coproc.c { CRn( 5), CRm( 1), Op1( 0), Op2( 0), is32, Op1 418 arch/arm/kvm/coproc.c { CRn( 5), CRm( 1), Op1( 0), Op2( 1), is32, Op1 422 arch/arm/kvm/coproc.c { CRn( 6), CRm( 0), Op1( 0), Op2( 0), is32, Op1 424 arch/arm/kvm/coproc.c { CRn( 6), CRm( 0), Op1( 0), Op2( 2), is32, Op1 428 arch/arm/kvm/coproc.c { CRm64( 7), Op1( 0), is64, NULL, reset_unknown64, c7_PAR }, Op1 433 arch/arm/kvm/coproc.c { CRn( 7), CRm( 6), Op1( 0), Op2( 2), is32, access_dcsw}, Op1 434 arch/arm/kvm/coproc.c { CRn( 7), CRm(10), Op1( 0), Op2( 2), is32, access_dcsw}, Op1 435 arch/arm/kvm/coproc.c { CRn( 7), CRm(14), Op1( 0), Op2( 2), is32, access_dcsw}, Op1 439 arch/arm/kvm/coproc.c { CRn( 9), CRm( 0), Op1( 1), Op2( 2), is32, Op1 441 arch/arm/kvm/coproc.c { CRn( 9), CRm( 0), Op1( 1), Op2( 3), is32, access_l2ectlr}, Op1 446 arch/arm/kvm/coproc.c { CRn( 9), CRm(12), Op1( 0), Op2( 0), is32, access_pmcr}, Op1 447 arch/arm/kvm/coproc.c { CRn( 9), CRm(12), Op1( 0), Op2( 1), is32, access_pmcntenset}, Op1 448 arch/arm/kvm/coproc.c { CRn( 9), CRm(12), Op1( 0), Op2( 2), is32, access_pmcntenclr}, Op1 449 arch/arm/kvm/coproc.c { CRn( 9), CRm(12), Op1( 0), Op2( 3), is32, access_pmovsr}, Op1 450 arch/arm/kvm/coproc.c { CRn( 9), CRm(12), Op1( 0), Op2( 5), is32, access_pmselr}, Op1 451 arch/arm/kvm/coproc.c { CRn( 9), CRm(12), Op1( 0), Op2( 6), is32, access_pmceid0}, Op1 452 arch/arm/kvm/coproc.c { CRn( 9), CRm(12), Op1( 0), Op2( 7), is32, access_pmceid1}, Op1 453 arch/arm/kvm/coproc.c { CRn( 9), CRm(13), Op1( 0), Op2( 0), is32, access_pmccntr}, Op1 454 arch/arm/kvm/coproc.c { CRn( 9), CRm(13), Op1( 0), Op2( 1), is32, access_pmxevtyper}, Op1 455 arch/arm/kvm/coproc.c { CRn( 9), CRm(13), Op1( 0), Op2( 2), is32, access_pmxevcntr}, Op1 456 arch/arm/kvm/coproc.c { CRn( 9), CRm(14), Op1( 0), Op2( 0), is32, access_pmuserenr}, Op1 457 arch/arm/kvm/coproc.c { CRn( 9), CRm(14), Op1( 0), Op2( 1), is32, access_pmintenset}, Op1 458 arch/arm/kvm/coproc.c { CRn( 9), CRm(14), Op1( 0), Op2( 2), is32, access_pmintenclr}, Op1 461 arch/arm/kvm/coproc.c { CRn(10), CRm( 2), Op1( 0), Op2( 0), is32, Op1 463 arch/arm/kvm/coproc.c { CRn(10), CRm( 2), Op1( 0), Op2( 1), is32, Op1 467 arch/arm/kvm/coproc.c { CRn(10), CRm( 3), Op1( 0), Op2( 0), is32, Op1 469 arch/arm/kvm/coproc.c { CRn(10), CRm( 3), Op1( 0), Op2( 1), is32, Op1 473 arch/arm/kvm/coproc.c { CRm64(12), Op1( 0), is64, access_gic_sgi}, Op1 476 arch/arm/kvm/coproc.c { CRn(12), CRm( 0), Op1( 0), Op2( 0), is32, Op1 480 arch/arm/kvm/coproc.c { CRm64(12), Op1( 1), is64, access_gic_sgi}, Op1 482 arch/arm/kvm/coproc.c { CRm64(12), Op1( 2), is64, access_gic_sgi}, Op1 484 arch/arm/kvm/coproc.c { CRn(12), CRm(12), Op1( 0), Op2(5), is32, access_gic_sre }, Op1 487 arch/arm/kvm/coproc.c { CRn(13), CRm( 0), Op1( 0), Op2( 1), is32, Op1 489 arch/arm/kvm/coproc.c { CRn(13), CRm( 0), Op1( 0), Op2( 2), is32, Op1 491 arch/arm/kvm/coproc.c { CRn(13), CRm( 0), Op1( 0), Op2( 3), is32, Op1 493 arch/arm/kvm/coproc.c { CRn(13), CRm( 0), Op1( 0), Op2( 4), is32, Op1 497 arch/arm/kvm/coproc.c { CRm64(14), Op1( 2), is64, access_cntp_cval}, Op1 500 arch/arm/kvm/coproc.c { CRn(14), CRm( 1), Op1( 0), Op2( 0), is32, Op1 504 arch/arm/kvm/coproc.c { CRn(14), CRm( 2), Op1( 0), Op2( 0), is32, access_cntp_tval }, Op1 505 arch/arm/kvm/coproc.c { CRn(14), CRm( 2), Op1( 0), Op2( 1), is32, access_cntp_ctl }, Op1 508 arch/arm/kvm/coproc.c { CRn(15), CRm( 0), Op1( 4), Op2( 0), is32, access_cbar}, Op1 549 arch/arm/kvm/coproc.c val |= (x)->Op1 << 4; \ Op1 578 arch/arm/kvm/coproc.c trace_kvm_emulate_cp15_imp(params->Op1, params->Rt1, params->CRn, Op1 616 arch/arm/kvm/coproc.c params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 16) & 0xf; Op1 682 arch/arm/kvm/coproc.c params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 14) & 0x7; Op1 739 arch/arm/kvm/coproc.c params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK) Op1 755 arch/arm/kvm/coproc.c params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK) Op1 837 arch/arm/kvm/coproc.c { CRn( 0), CRm( 0), Op1( 0), Op2( 0), is32, NULL, get_MIDR }, Op1 838 arch/arm/kvm/coproc.c { CRn( 0), CRm( 0), Op1( 0), Op2( 1), is32, NULL, get_CTR }, Op1 839 arch/arm/kvm/coproc.c { CRn( 0), CRm( 0), Op1( 0), Op2( 2), is32, NULL, get_TCMTR }, Op1 840 arch/arm/kvm/coproc.c { CRn( 0), CRm( 0), Op1( 0), Op2( 3), is32, NULL, get_TLBTR }, Op1 841 arch/arm/kvm/coproc.c { CRn( 0), CRm( 0), Op1( 0), Op2( 6), is32, NULL, get_REVIDR }, Op1 843 arch/arm/kvm/coproc.c { CRn( 0), CRm( 0), Op1( 1), Op2( 1), is32, NULL, get_CLIDR }, Op1 844 arch/arm/kvm/coproc.c { CRn( 0), CRm( 0), Op1( 1), Op2( 7), is32, NULL, get_AIDR }, Op1 846 arch/arm/kvm/coproc.c { CRn( 0), CRm( 1), Op1( 0), Op2( 0), is32, NULL, get_ID_PFR0 }, Op1 847 arch/arm/kvm/coproc.c { CRn( 0), CRm( 1), Op1( 0), Op2( 1), is32, NULL, get_ID_PFR1 }, Op1 848 arch/arm/kvm/coproc.c { CRn( 0), CRm( 1), Op1( 0), Op2( 2), is32, NULL, get_ID_DFR0 }, Op1 849 arch/arm/kvm/coproc.c { CRn( 0), CRm( 1), Op1( 0), Op2( 3), is32, NULL, get_ID_AFR0 }, Op1 850 arch/arm/kvm/coproc.c { CRn( 0), CRm( 1), Op1( 0), Op2( 4), is32, NULL, get_ID_MMFR0 }, Op1 851 arch/arm/kvm/coproc.c { CRn( 0), CRm( 1), Op1( 0), Op2( 5), is32, NULL, get_ID_MMFR1 }, Op1 852 arch/arm/kvm/coproc.c { CRn( 0), CRm( 1), Op1( 0), Op2( 6), is32, NULL, get_ID_MMFR2 }, Op1 853 arch/arm/kvm/coproc.c { CRn( 0), CRm( 1), Op1( 0), Op2( 7), is32, NULL, get_ID_MMFR3 }, Op1 855 arch/arm/kvm/coproc.c { CRn( 0), CRm( 2), Op1( 0), Op2( 0), is32, NULL, get_ID_ISAR0 }, Op1 856 arch/arm/kvm/coproc.c { CRn( 0), CRm( 2), Op1( 0), Op2( 1), is32, NULL, get_ID_ISAR1 }, Op1 857 arch/arm/kvm/coproc.c { CRn( 0), CRm( 2), Op1( 0), Op2( 2), is32, NULL, get_ID_ISAR2 }, Op1 858 arch/arm/kvm/coproc.c { CRn( 0), CRm( 2), Op1( 0), Op2( 3), is32, NULL, get_ID_ISAR3 }, Op1 859 arch/arm/kvm/coproc.c { CRn( 0), CRm( 2), Op1( 0), Op2( 4), is32, NULL, get_ID_ISAR4 }, Op1 860 arch/arm/kvm/coproc.c { CRn( 0), CRm( 2), Op1( 0), Op2( 5), is32, NULL, get_ID_ISAR5 }, Op1 1296 arch/arm/kvm/coproc.c val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT); Op1 1307 arch/arm/kvm/coproc.c val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT); Op1 13 arch/arm/kvm/coproc.h unsigned long Op1; Op1 25 arch/arm/kvm/coproc.h unsigned long Op1; Op1 50 arch/arm/kvm/coproc.h p->CRn, p->Op1, p->is_write ? "write" : "read"); Op1 54 arch/arm/kvm/coproc.h p->CRn, p->CRm, p->Op1, p->Op2, Op1 110 arch/arm/kvm/coproc.h if (i1->Op1 != i2->Op1) Op1 111 arch/arm/kvm/coproc.h return i1->Op1 - i2->Op1; Op1 121 arch/arm/kvm/coproc.h #define Op1(_x) .Op1 = _x Op1 24 arch/arm/kvm/coproc_a15.c { CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32, Op1 27 arch/arm/kvm/coproc_a7.c { CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32, Op1 12 arch/arm/kvm/trace.h TP_PROTO(unsigned long Op1, unsigned long Rt1, unsigned long CRn, Op1 14 arch/arm/kvm/trace.h TP_ARGS(Op1, Rt1, CRn, CRm, Op2, is_write), Op1 17 arch/arm/kvm/trace.h __field( unsigned int, Op1 ) Op1 27 arch/arm/kvm/trace.h __entry->Op1 = Op1; Op1 36 arch/arm/kvm/trace.h __entry->Op1, __entry->Rt1, __entry->CRn, Op1 257 arch/arm64/kvm/sys_regs.c switch (p->Op1) { Op1 317 arch/arm64/kvm/sys_regs.c u32 sr = sys_reg((u32)r->Op0, (u32)r->Op1, Op1 982 arch/arm64/kvm/sys_regs.c sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \ Op1 1077 arch/arm64/kvm/sys_regs.c u32 id = sys_reg((u32)r->Op0, (u32)r->Op1, Op1 1338 arch/arm64/kvm/sys_regs.c Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ Op1 1722 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \ Op1 1724 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \ Op1 1726 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \ Op1 1728 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n } Op1 1731 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n } Op1 1740 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr }, Op1 1742 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, Op1 1746 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, Op1 1749 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 }, Op1 1751 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 }, Op1 1754 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, Op1 1756 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, Op1 1761 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, Op1 1763 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, Op1 1766 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 }, Op1 1778 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, Op1 1782 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi }, Op1 1785 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 }, Op1 1789 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, Op1 1792 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, Op1 1806 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, Op1 1809 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, Op1 1811 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, Op1 1813 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, Op1 1815 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, Op1 1817 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, Op1 1819 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, Op1 1825 arch/arm64/kvm/sys_regs.c { Op1( 0), CRm( 1), .access = trap_raz_wi }, Op1 1828 arch/arm64/kvm/sys_regs.c { Op1( 0), CRm( 2), .access = trap_raz_wi }, Op1 1834 arch/arm64/kvm/sys_regs.c { Op1(0), CRn(0b1110), \ Op1 1841 arch/arm64/kvm/sys_regs.c { Op1(0), CRn(0b1110), \ Op1 1851 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, Op1 1852 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR }, Op1 1853 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 }, Op1 1854 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 }, Op1 1855 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR }, Op1 1856 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR }, Op1 1857 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR }, Op1 1858 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR }, Op1 1859 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR }, Op1 1860 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR }, Op1 1861 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR }, Op1 1862 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR }, Op1 1867 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, Op1 1868 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, Op1 1869 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, Op1 1872 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr }, Op1 1873 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten }, Op1 1874 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten }, Op1 1875 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs }, Op1 1876 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc }, Op1 1877 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr }, Op1 1878 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid }, Op1 1879 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid }, Op1 1880 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr }, Op1 1881 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper }, Op1 1882 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr }, Op1 1883 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr }, Op1 1884 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten }, Op1 1885 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten }, Op1 1886 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs }, Op1 1888 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR }, Op1 1889 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR }, Op1 1890 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 }, Op1 1891 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 }, Op1 1894 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre }, Op1 1896 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID }, Op1 1967 arch/arm64/kvm/sys_regs.c { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper }, Op1 1969 arch/arm64/kvm/sys_regs.c { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, Op1 1970 arch/arm64/kvm/sys_regs.c { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, Op1 1971 arch/arm64/kvm/sys_regs.c { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, c0_CSSELR }, Op1 1975 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 }, Op1 1976 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr }, Op1 1977 arch/arm64/kvm/sys_regs.c { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ Op1 1978 arch/arm64/kvm/sys_regs.c { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 }, Op1 1979 arch/arm64/kvm/sys_regs.c { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ Op1 1980 arch/arm64/kvm/sys_regs.c { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ Op1 2135 arch/arm64/kvm/sys_regs.c params.Op1 = (hsr >> 16) & 0xf; Op1 2192 arch/arm64/kvm/sys_regs.c params.Op1 = (hsr >> 14) & 0x7; Op1 2299 arch/arm64/kvm/sys_regs.c params.Op1 = (esr >> 14) & 0x7; Op1 2332 arch/arm64/kvm/sys_regs.c params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) Op1 2632 arch/arm64/kvm/sys_regs.c (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | Op1 16 arch/arm64/kvm/sys_regs.h u8 Op1; Op1 32 arch/arm64/kvm/sys_regs.h u8 Op1; Op1 69 arch/arm64/kvm/sys_regs.h p->Op0, p->Op1, p->CRn, p->CRm, p->Op2, p->is_write ? "write" : "read"); Op1 129 arch/arm64/kvm/sys_regs.h if (i1->Op1 != i2->Op1) Op1 130 arch/arm64/kvm/sys_regs.h return i1->Op1 - i2->Op1; Op1 144 arch/arm64/kvm/sys_regs.h #define Op1(_x) .Op1 = _x Op1 151 arch/arm64/kvm/sys_regs.h Op0(sys_reg_Op0(reg)), Op1(sys_reg_Op1(reg)), \ Op1 49 arch/arm64/kvm/sys_regs_generic_v8.c { Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b001), Op1 165 arch/arm64/kvm/trace.h __field(u8, Op1) Op1 177 arch/arm64/kvm/trace.h __entry->Op1 = reg->Op1; Op1 185 arch/arm64/kvm/trace.h __entry->Op0, __entry->Op1, __entry->CRn,