OTG_H_TIMING_DIV_BY2 292 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c OTG_H_TIMING_DIV_BY2, h_div); OTG_H_TIMING_DIV_BY2 196 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_BY2, mask_sh),\ OTG_H_TIMING_DIV_BY2 334 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h type OTG_H_TIMING_DIV_BY2;\ OTG_H_TIMING_DIV_BY2 226 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c OTG_H_TIMING_DIV_BY2, h_div_2); OTG_H_TIMING_DIV_BY2 277 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1);