OTG 20 arch/arm/mach-imx/devices/platform-mxc-ehci.c imx_mxc_ehci_data_entry_single(MX27, 0, OTG); OTG 29 arch/arm/mach-imx/devices/platform-mxc-ehci.c imx_mxc_ehci_data_entry_single(MX31, 0, OTG); OTG 38 arch/arm/mach-imx/devices/platform-mxc-ehci.c imx_mxc_ehci_data_entry_single(MX35, 0, OTG); OTG 73 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PIXEL_RATE_CNTL, OTG, 0),\ OTG 74 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PIXEL_RATE_CNTL, OTG, 1),\ OTG 75 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PIXEL_RATE_CNTL, OTG, 2),\ OTG 76 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PIXEL_RATE_CNTL, OTG, 3),\ OTG 77 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PIXEL_RATE_CNTL, OTG, 4),\ OTG 78 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PIXEL_RATE_CNTL, OTG, 5) OTG 92 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PIXEL_RATE_CNTL, OTG, 0),\ OTG 93 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PIXEL_RATE_CNTL, OTG, 1),\ OTG 94 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PIXEL_RATE_CNTL, OTG, 2),\ OTG 95 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PIXEL_RATE_CNTL, OTG, 3) OTG 118 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PIXEL_RATE_CNTL, OTG, 0), \ OTG 119 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PIXEL_RATE_CNTL, OTG, 1), \ OTG 120 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PIXEL_RATE_CNTL, OTG, 2), \ OTG 121 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h SRII(PIXEL_RATE_CNTL, OTG, 3) OTG 180 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ OTG 181 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ OTG 182 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ OTG 183 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ OTG 216 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ OTG 217 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ OTG 218 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ OTG 219 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ OTG 220 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 4), \ OTG 221 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 5), \ OTG 284 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ OTG 285 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ OTG 286 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ OTG 287 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ OTG 35 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_VSTARTUP_PARAM, OTG, inst),\ OTG 36 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_VUPDATE_PARAM, OTG, inst),\ OTG 37 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_VREADY_PARAM, OTG, inst),\ OTG 38 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_BLANK_CONTROL, OTG, inst),\ OTG 39 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\ OTG 40 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\ OTG 41 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\ OTG 42 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_H_TOTAL, OTG, inst),\ OTG 43 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_H_BLANK_START_END, OTG, inst),\ OTG 44 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_H_SYNC_A, OTG, inst),\ OTG 45 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\ OTG 46 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_H_TIMING_CNTL, OTG, inst),\ OTG 47 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_V_TOTAL, OTG, inst),\ OTG 48 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_V_BLANK_START_END, OTG, inst),\ OTG 49 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_V_SYNC_A, OTG, inst),\ OTG 50 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\ OTG 51 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_INTERLACE_CONTROL, OTG, inst),\ OTG 52 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_CONTROL, OTG, inst),\ OTG 53 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_STEREO_CONTROL, OTG, inst),\ OTG 54 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\ OTG 55 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_STEREO_STATUS, OTG, inst),\ OTG 56 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_V_TOTAL_MAX, OTG, inst),\ OTG 57 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_V_TOTAL_MID, OTG, inst),\ OTG 58 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_V_TOTAL_MIN, OTG, inst),\ OTG 59 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\ OTG 60 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_TRIGA_CNTL, OTG, inst),\ OTG 61 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\ OTG 62 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\ OTG 63 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\ OTG 64 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_STATUS, OTG, inst),\ OTG 65 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_STATUS_POSITION, OTG, inst),\ OTG 66 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_NOM_VERT_POSITION, OTG, inst),\ OTG 67 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_BLACK_COLOR, OTG, inst),\ OTG 68 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_CLOCK_CONTROL, OTG, inst),\ OTG 69 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\ OTG 70 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\ OTG 71 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\ OTG 72 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\ OTG 73 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\ OTG 74 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\ OTG 79 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\ OTG 80 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_MASTER_UPDATE_MODE, OTG, inst),\ OTG 81 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_GSL_CONTROL, OTG, inst),\ OTG 82 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_CRC_CNTL, OTG, inst),\ OTG 83 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_CRC0_DATA_RG, OTG, inst),\ OTG 84 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_CRC0_DATA_B, OTG, inst),\ OTG 85 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\ OTG 86 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\ OTG 87 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\ OTG 88 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\ OTG 90 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\ OTG 91 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst) OTG 95 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\ OTG 96 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\ OTG 97 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_TEST_PATTERN_COLOR, OTG, inst),\ OTG 98 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst) OTG 33 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\ OTG 34 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\ OTG 35 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SRI(OTG_GSL_WINDOW_X, OTG, inst),\ OTG 36 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SRI(OTG_GSL_WINDOW_Y, OTG, inst),\ OTG 37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\ OTG 38 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SRI(OTG_DSC_START_POSITION, OTG, inst),\ OTG 44 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst) OTG 230 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c IRQ_REG_ENTRY(OTG, reg_num,\ OTG 238 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c IRQ_REG_ENTRY(OTG, reg_num,\ OTG 234 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c IRQ_REG_ENTRY(OTG, reg_num,\ OTG 242 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c IRQ_REG_ENTRY(OTG, reg_num,\ OTG 227 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c IRQ_REG_ENTRY(OTG, reg_num,\ OTG 235 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c IRQ_REG_ENTRY(OTG, reg_num,\ OTG 1451 drivers/regulator/qcom_spmi-regulator.c SPMI_VREG_VS(OTG, 0, INF), OTG 567 drivers/usb/phy/phy-isp1301-omap.c # define toggle(OTG,ISP) do { \ OTG 568 drivers/usb/phy/phy-isp1301-omap.c if (otg_ctrl & OTG) set |= ISP; \