ORION5X_BRIDGE_VIRT_BASE   14 arch/arm/mach-orion5x/bridge-regs.h #define CPU_CONF		(ORION5X_BRIDGE_VIRT_BASE + 0x100)
ORION5X_BRIDGE_VIRT_BASE   16 arch/arm/mach-orion5x/bridge-regs.h #define CPU_CTRL		(ORION5X_BRIDGE_VIRT_BASE + 0x104)
ORION5X_BRIDGE_VIRT_BASE   18 arch/arm/mach-orion5x/bridge-regs.h #define RSTOUTn_MASK		(ORION5X_BRIDGE_VIRT_BASE + 0x108)
ORION5X_BRIDGE_VIRT_BASE   21 arch/arm/mach-orion5x/bridge-regs.h #define CPU_SOFT_RESET		(ORION5X_BRIDGE_VIRT_BASE + 0x10c)
ORION5X_BRIDGE_VIRT_BASE   23 arch/arm/mach-orion5x/bridge-regs.h #define BRIDGE_CAUSE		(ORION5X_BRIDGE_VIRT_BASE + 0x110)
ORION5X_BRIDGE_VIRT_BASE   25 arch/arm/mach-orion5x/bridge-regs.h #define POWER_MNG_CTRL_REG	(ORION5X_BRIDGE_VIRT_BASE + 0x11C)
ORION5X_BRIDGE_VIRT_BASE   29 arch/arm/mach-orion5x/bridge-regs.h #define MAIN_IRQ_CAUSE		(ORION5X_BRIDGE_VIRT_BASE + 0x200)
ORION5X_BRIDGE_VIRT_BASE   31 arch/arm/mach-orion5x/bridge-regs.h #define MAIN_IRQ_MASK		(ORION5X_BRIDGE_VIRT_BASE + 0x204)
ORION5X_BRIDGE_VIRT_BASE   33 arch/arm/mach-orion5x/bridge-regs.h #define TIMER_VIRT_BASE		(ORION5X_BRIDGE_VIRT_BASE + 0x300)
ORION5X_BRIDGE_VIRT_BASE  276 arch/arm/mach-orion5x/common.c 	orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,