OPP_SF 88 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\ OPP_SF 89 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\ OPP_SF 90 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\ OPP_SF 91 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\ OPP_SF 92 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\ OPP_SF 93 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\ OPP_SF 94 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\ OPP_SF 95 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\ OPP_SF 96 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\ OPP_SF 97 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\ OPP_SF 98 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\ OPP_SF 99 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ OPP_SF 100 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\ OPP_SF 101 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\ OPP_SF 102 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\ OPP_SF 103 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ OPP_SF 104 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\ OPP_SF 105 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\ OPP_SF 106 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\ OPP_SF 107 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\ OPP_SF 108 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\ OPP_SF 109 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\ OPP_SF 110 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\ OPP_SF 111 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\ OPP_SF 112 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\ OPP_SF 113 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh),\ OPP_SF 114 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CLAMP_COMPONENT_R, FMT_CLAMP_LOWER_R, mask_sh),\ OPP_SF 115 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CLAMP_COMPONENT_R, FMT_CLAMP_UPPER_R, mask_sh),\ OPP_SF 116 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CLAMP_COMPONENT_G, FMT_CLAMP_LOWER_G, mask_sh),\ OPP_SF 117 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CLAMP_COMPONENT_G, FMT_CLAMP_UPPER_G, mask_sh),\ OPP_SF 118 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CLAMP_COMPONENT_B, FMT_CLAMP_LOWER_B, mask_sh),\ OPP_SF 119 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CLAMP_COMPONENT_B, FMT_CLAMP_UPPER_B, mask_sh),\ OPP_SF 120 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\ OPP_SF 121 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\ OPP_SF 122 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh) OPP_SF 126 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ OPP_SF 127 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ OPP_SF 128 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) OPP_SF 132 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ OPP_SF 133 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ OPP_SF 134 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) OPP_SF 138 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_SOURCE_SEL, mask_sh),\ OPP_SF 139 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_PWR_FORCE, mask_sh),\ OPP_SF 140 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED_CLEAR, mask_sh),\ OPP_SF 141 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, mask_sh),\ OPP_SF 142 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh),\ OPP_SF 143 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ OPP_SF 144 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ OPP_SF 145 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) OPP_SF 151 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\ OPP_SF 152 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\ OPP_SF 153 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\ OPP_SF 154 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\ OPP_SF 155 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\ OPP_SF 156 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\ OPP_SF 157 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\ OPP_SF 158 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\ OPP_SF 159 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ OPP_SF 160 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\ OPP_SF 161 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\ OPP_SF 162 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\ OPP_SF 163 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\ OPP_SF 164 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\ OPP_SF 165 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\ OPP_SF 166 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\ OPP_SF 167 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\ OPP_SF 168 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\ OPP_SF 169 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\ OPP_SF 170 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ OPP_SF 171 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ OPP_SF 172 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ OPP_SF 173 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh),\ OPP_SF 174 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\ OPP_SF 175 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\ OPP_SF 176 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\ OPP_SF 177 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_SOURCE_SEL, mask_sh),\ OPP_SF 178 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_PWR_FORCE, mask_sh),\ OPP_SF 179 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\ OPP_SF 180 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED_CLEAR, mask_sh),\ OPP_SF 181 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, mask_sh),\ OPP_SF 182 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\ OPP_SF 183 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh),\ OPP_SF 184 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CLAMP_COMPONENT_R, FMT_CLAMP_LOWER_R, mask_sh),\ OPP_SF 185 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CLAMP_COMPONENT_R, FMT_CLAMP_UPPER_R, mask_sh),\ OPP_SF 186 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CLAMP_COMPONENT_G, FMT_CLAMP_LOWER_G, mask_sh),\ OPP_SF 187 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CLAMP_COMPONENT_G, FMT_CLAMP_UPPER_G, mask_sh),\ OPP_SF 188 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CLAMP_COMPONENT_B, FMT_CLAMP_LOWER_B, mask_sh),\ OPP_SF 189 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CLAMP_COMPONENT_B, FMT_CLAMP_UPPER_B, mask_sh),\ OPP_SF 190 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\ OPP_SF 191 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\ OPP_SF 192 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh),\ OPP_SF 193 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh) OPP_SF 194 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_LIGHT_SLEEP_DIS, mask_sh),\ OPP_SF 195 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, DCP_LUT_LIGHT_SLEEP_DIS, mask_sh),\ OPP_SF 196 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, mask_sh) OPP_SF 69 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \ OPP_SF 70 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh), \ OPP_SF 71 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh), \ OPP_SF 72 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh), \ OPP_SF 73 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh), \ OPP_SF 74 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh), \ OPP_SF 75 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh), \ OPP_SF 76 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh), \ OPP_SF 77 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh), \ OPP_SF 78 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh), \ OPP_SF 79 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh), \ OPP_SF 80 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh), \ OPP_SF 81 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh), \ OPP_SF 82 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh), \ OPP_SF 83 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh), \ OPP_SF 84 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh), \ OPP_SF 85 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh), \ OPP_SF 86 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh), \ OPP_SF 87 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh), \ OPP_SF 88 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh), \ OPP_SF 89 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh), \ OPP_SF 90 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(FMT0_FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, mask_sh), \ OPP_SF 91 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, mask_sh),\ OPP_SF 92 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_PIXEL_REPETITION, mask_sh),\ OPP_SF 93 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, mask_sh), \ OPP_SF 94 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE2_SIZE, mask_sh), \ OPP_SF 95 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(OPP_PIPE0_OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, mask_sh) OPP_SF 99 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_DISPLAY_SEGMENTATION, mask_sh),\ OPP_SF 100 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_OVERLAP_PIXEL_NUM, mask_sh) OPP_SF 63 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_CONTROL, DPG_EN, mask_sh), \ OPP_SF 64 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_CONTROL, DPG_MODE, mask_sh), \ OPP_SF 65 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_CONTROL, DPG_DYNAMIC_RANGE, mask_sh), \ OPP_SF 66 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_CONTROL, DPG_BIT_DEPTH, mask_sh), \ OPP_SF 67 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_CONTROL, DPG_VRES, mask_sh), \ OPP_SF 68 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_CONTROL, DPG_HRES, mask_sh), \ OPP_SF 69 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_DIMENSIONS, DPG_ACTIVE_WIDTH, mask_sh), \ OPP_SF 70 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_DIMENSIONS, DPG_ACTIVE_HEIGHT, mask_sh), \ OPP_SF 71 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_COLOUR_R_CR, DPG_COLOUR0_R_CR, mask_sh), \ OPP_SF 72 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_COLOUR_R_CR, DPG_COLOUR1_R_CR, mask_sh), \ OPP_SF 73 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_COLOUR_B_CB, DPG_COLOUR0_B_CB, mask_sh), \ OPP_SF 74 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_COLOUR_B_CB, DPG_COLOUR1_B_CB, mask_sh), \ OPP_SF 75 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_COLOUR_G_Y, DPG_COLOUR0_G_Y, mask_sh), \ OPP_SF 76 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_COLOUR_G_Y, DPG_COLOUR1_G_Y, mask_sh), \ OPP_SF 77 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_RAMP_CONTROL, DPG_RAMP0_OFFSET, mask_sh), \ OPP_SF 78 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_RAMP_CONTROL, DPG_INC0, mask_sh), \ OPP_SF 79 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_RAMP_CONTROL, DPG_INC1, mask_sh), \ OPP_SF 80 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(DPG0_DPG_STATUS, DPG_DOUBLE_BUFFER_PENDING, mask_sh) OPP_SF 85 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_DISPLAY_SEGMENTATION, mask_sh),\ OPP_SF 86 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_OVERLAP_PIXEL_NUM, mask_sh), \ OPP_SF 87 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h OPP_SF(FMT0_FMT_422_CONTROL, FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT, mask_sh)