OPCODE1            46 arch/parisc/kernel/unaligned.c #define OPCODE1_MASK	OPCODE1(0x3f,1,0xf)
OPCODE1            52 arch/parisc/kernel/unaligned.c #define OPCODE_LDH_I	OPCODE1(0x03,0,0x1)
OPCODE1            53 arch/parisc/kernel/unaligned.c #define OPCODE_LDW_I	OPCODE1(0x03,0,0x2)
OPCODE1            54 arch/parisc/kernel/unaligned.c #define OPCODE_LDD_I	OPCODE1(0x03,0,0x3)
OPCODE1            55 arch/parisc/kernel/unaligned.c #define OPCODE_LDDA_I	OPCODE1(0x03,0,0x4)
OPCODE1            56 arch/parisc/kernel/unaligned.c #define OPCODE_LDCD_I	OPCODE1(0x03,0,0x5)
OPCODE1            57 arch/parisc/kernel/unaligned.c #define OPCODE_LDWA_I	OPCODE1(0x03,0,0x6)
OPCODE1            58 arch/parisc/kernel/unaligned.c #define OPCODE_LDCW_I	OPCODE1(0x03,0,0x7)
OPCODE1            60 arch/parisc/kernel/unaligned.c #define OPCODE_LDH_S	OPCODE1(0x03,1,0x1)
OPCODE1            61 arch/parisc/kernel/unaligned.c #define OPCODE_LDW_S	OPCODE1(0x03,1,0x2)
OPCODE1            62 arch/parisc/kernel/unaligned.c #define OPCODE_LDD_S	OPCODE1(0x03,1,0x3)
OPCODE1            63 arch/parisc/kernel/unaligned.c #define OPCODE_LDDA_S	OPCODE1(0x03,1,0x4)
OPCODE1            64 arch/parisc/kernel/unaligned.c #define OPCODE_LDCD_S	OPCODE1(0x03,1,0x5)
OPCODE1            65 arch/parisc/kernel/unaligned.c #define OPCODE_LDWA_S	OPCODE1(0x03,1,0x6)
OPCODE1            66 arch/parisc/kernel/unaligned.c #define OPCODE_LDCW_S	OPCODE1(0x03,1,0x7)
OPCODE1            68 arch/parisc/kernel/unaligned.c #define OPCODE_STH	OPCODE1(0x03,1,0x9)
OPCODE1            69 arch/parisc/kernel/unaligned.c #define OPCODE_STW	OPCODE1(0x03,1,0xa)
OPCODE1            70 arch/parisc/kernel/unaligned.c #define OPCODE_STD	OPCODE1(0x03,1,0xb)
OPCODE1            73 arch/parisc/kernel/unaligned.c #define OPCODE_STWA	OPCODE1(0x03,1,0xe)
OPCODE1            74 arch/parisc/kernel/unaligned.c #define OPCODE_STDA	OPCODE1(0x03,1,0xf)
OPCODE1            76 arch/parisc/kernel/unaligned.c #define OPCODE_FLDWX	OPCODE1(0x09,0,0x0)
OPCODE1            77 arch/parisc/kernel/unaligned.c #define OPCODE_FLDWXR	OPCODE1(0x09,0,0x1)
OPCODE1            78 arch/parisc/kernel/unaligned.c #define OPCODE_FSTWX	OPCODE1(0x09,0,0x8)
OPCODE1            79 arch/parisc/kernel/unaligned.c #define OPCODE_FSTWXR	OPCODE1(0x09,0,0x9)
OPCODE1            80 arch/parisc/kernel/unaligned.c #define OPCODE_FLDWS	OPCODE1(0x09,1,0x0)
OPCODE1            81 arch/parisc/kernel/unaligned.c #define OPCODE_FLDWSR	OPCODE1(0x09,1,0x1)
OPCODE1            82 arch/parisc/kernel/unaligned.c #define OPCODE_FSTWS	OPCODE1(0x09,1,0x8)
OPCODE1            83 arch/parisc/kernel/unaligned.c #define OPCODE_FSTWSR	OPCODE1(0x09,1,0x9)
OPCODE1            84 arch/parisc/kernel/unaligned.c #define OPCODE_FLDDX	OPCODE1(0x0b,0,0x0)
OPCODE1            85 arch/parisc/kernel/unaligned.c #define OPCODE_FSTDX	OPCODE1(0x0b,0,0x8)
OPCODE1            86 arch/parisc/kernel/unaligned.c #define OPCODE_FLDDS	OPCODE1(0x0b,1,0x0)
OPCODE1            87 arch/parisc/kernel/unaligned.c #define OPCODE_FSTDS	OPCODE1(0x0b,1,0x8)
OPCODE1           298 arch/x86/kernel/uprobes.c 	if (test_bit(OPCODE1(insn), (unsigned long *)good_insns))
OPCODE1           717 arch/x86/kernel/uprobes.c 	u8 opc1 = OPCODE1(insn);
OPCODE1           765 arch/x86/kernel/uprobes.c 	u8 opc1 = OPCODE1(insn), reg_offset = 0;
OPCODE1           872 arch/x86/kernel/uprobes.c 	switch (OPCODE1(&insn)) {