OP2 106 arch/arm/include/asm/hw_breakpoint.h #define ARM_DBG_READ(N, M, OP2, VAL) do {\ OP2 107 arch/arm/include/asm/hw_breakpoint.h asm volatile("mrc p14, 0, %0, " #N "," #M ", " #OP2 : "=r" (VAL));\ OP2 110 arch/arm/include/asm/hw_breakpoint.h #define ARM_DBG_WRITE(N, M, OP2, VAL) do {\ OP2 111 arch/arm/include/asm/hw_breakpoint.h asm volatile("mcr p14, 0, %0, " #N "," #M ", " #OP2 : : "r" (VAL));\ OP2 48 arch/arm/kernel/hw_breakpoint.c #define READ_WB_REG_CASE(OP2, M, VAL) \ OP2 49 arch/arm/kernel/hw_breakpoint.c case ((OP2 << 4) + M): \ OP2 50 arch/arm/kernel/hw_breakpoint.c ARM_DBG_READ(c0, c ## M, OP2, VAL); \ OP2 53 arch/arm/kernel/hw_breakpoint.c #define WRITE_WB_REG_CASE(OP2, M, VAL) \ OP2 54 arch/arm/kernel/hw_breakpoint.c case ((OP2 << 4) + M): \ OP2 55 arch/arm/kernel/hw_breakpoint.c ARM_DBG_WRITE(c0, c ## M, OP2, VAL); \ OP2 58 arch/arm/kernel/hw_breakpoint.c #define GEN_READ_WB_REG_CASES(OP2, VAL) \ OP2 59 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 0, VAL); \ OP2 60 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 1, VAL); \ OP2 61 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 2, VAL); \ OP2 62 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 3, VAL); \ OP2 63 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 4, VAL); \ OP2 64 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 5, VAL); \ OP2 65 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 6, VAL); \ OP2 66 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 7, VAL); \ OP2 67 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 8, VAL); \ OP2 68 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 9, VAL); \ OP2 69 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 10, VAL); \ OP2 70 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 11, VAL); \ OP2 71 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 12, VAL); \ OP2 72 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 13, VAL); \ OP2 73 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 14, VAL); \ OP2 74 arch/arm/kernel/hw_breakpoint.c READ_WB_REG_CASE(OP2, 15, VAL) OP2 76 arch/arm/kernel/hw_breakpoint.c #define GEN_WRITE_WB_REG_CASES(OP2, VAL) \ OP2 77 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 0, VAL); \ OP2 78 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 1, VAL); \ OP2 79 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 2, VAL); \ OP2 80 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 3, VAL); \ OP2 81 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 4, VAL); \ OP2 82 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 5, VAL); \ OP2 83 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 6, VAL); \ OP2 84 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 7, VAL); \ OP2 85 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 8, VAL); \ OP2 86 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 9, VAL); \ OP2 87 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 10, VAL); \ OP2 88 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 11, VAL); \ OP2 89 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 12, VAL); \ OP2 90 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 13, VAL); \ OP2 91 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 14, VAL); \ OP2 92 arch/arm/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OP2, 15, VAL) OP2 213 arch/arm64/include/uapi/asm/kvm.h ARM64_SYS_REG_SHIFT_MASK(op2, OP2)) OP2 33 arch/sparc/net/bpf_jit_comp_32.c #define F2(X, Y) (OP(X) | OP2(Y)) OP2 63 arch/sparc/net/bpf_jit_comp_64.c #define F2(X, Y) (OP(X) | OP2(Y)) OP2 1517 fs/afs/internal.h #define ASSERTRANGE(L, OP1, N, OP2, H) \ OP2 1519 fs/afs/internal.h if (unlikely(!((L) OP1 (N)) || !((N) OP2 (H)))) { \ OP2 1522 fs/afs/internal.h printk(KERN_ERR "%lu "#OP1" %lu "#OP2" %lu is false\n", \ OP2 1525 fs/afs/internal.h printk(KERN_ERR "0x%lx "#OP1" 0x%lx "#OP2" 0x%lx is false\n", \ OP2 1564 fs/afs/internal.h #define ASSERTRANGE(L, OP1, N, OP2, H) \ OP2 213 tools/arch/arm64/include/uapi/asm/kvm.h ARM64_SYS_REG_SHIFT_MASK(op2, OP2))