OMAP_IH2_BASE 32 arch/arm/mach-omap1/ams-delta-fiq.h #define DEFERRED_FIQ_IH_BASE OMAP_IH2_BASE OMAP_IH2_BASE 197 arch/arm/mach-omap1/include/mach/hardware.h #define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00) OMAP_IH2_BASE 198 arch/arm/mach-omap1/include/mach/hardware.h #define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04) OMAP_IH2_BASE 199 arch/arm/mach-omap1/include/mach/hardware.h #define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10) OMAP_IH2_BASE 200 arch/arm/mach-omap1/include/mach/hardware.h #define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14) OMAP_IH2_BASE 201 arch/arm/mach-omap1/include/mach/hardware.h #define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18) OMAP_IH2_BASE 202 arch/arm/mach-omap1/include/mach/hardware.h #define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c) OMAP_IH2_BASE 203 arch/arm/mach-omap1/include/mach/hardware.h #define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c) OMAP_IH2_BASE 118 arch/arm/mach-omap1/irq.c { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 }, OMAP_IH2_BASE 119 arch/arm/mach-omap1/irq.c { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 }, OMAP_IH2_BASE 126 arch/arm/mach-omap1/irq.c { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed }, OMAP_IH2_BASE 130 arch/arm/mach-omap1/irq.c { .base_reg = OMAP_IH2_BASE, .trigger_map = 0x65b3c061 }, OMAP_IH2_BASE 138 arch/arm/mach-omap1/irq.c { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd }, OMAP_IH2_BASE 139 arch/arm/mach-omap1/irq.c { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0xffffb7ff }, OMAP_IH2_BASE 140 arch/arm/mach-omap1/irq.c { .base_reg = OMAP_IH2_BASE + 0x200, .trigger_map = 0xffffffff },