OMAP_IH1_BASE 198 arch/arm/mach-omap1/ams-delta-fiq.c val = omap_readl(OMAP_IH1_BASE + offset) | 1; OMAP_IH1_BASE 199 arch/arm/mach-omap1/ams-delta-fiq.c omap_writel(val, OMAP_IH1_BASE + offset); OMAP_IH1_BASE 30 arch/arm/mach-omap1/ams-delta-fiq.h #define DEFERRED_FIQ_IH_BASE OMAP_IH1_BASE OMAP_IH1_BASE 189 arch/arm/mach-omap1/include/mach/hardware.h #define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00) OMAP_IH1_BASE 190 arch/arm/mach-omap1/include/mach/hardware.h #define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04) OMAP_IH1_BASE 191 arch/arm/mach-omap1/include/mach/hardware.h #define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10) OMAP_IH1_BASE 192 arch/arm/mach-omap1/include/mach/hardware.h #define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14) OMAP_IH1_BASE 193 arch/arm/mach-omap1/include/mach/hardware.h #define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18) OMAP_IH1_BASE 194 arch/arm/mach-omap1/include/mach/hardware.h #define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c) OMAP_IH1_BASE 195 arch/arm/mach-omap1/include/mach/hardware.h #define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c) OMAP_IH1_BASE 117 arch/arm/mach-omap1/irq.c { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f }, OMAP_IH1_BASE 125 arch/arm/mach-omap1/irq.c { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff }, OMAP_IH1_BASE 129 arch/arm/mach-omap1/irq.c { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3faefc3 }, OMAP_IH1_BASE 137 arch/arm/mach-omap1/irq.c { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f },