OMAP_DMA_REG_32BIT   39 arch/arm/mach-omap2/dma.c 	[REVISION]	= { 0x0000, 0x00, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   40 arch/arm/mach-omap2/dma.c 	[GCR]		= { 0x0078, 0x00, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   41 arch/arm/mach-omap2/dma.c 	[IRQSTATUS_L0]	= { 0x0008, 0x00, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   42 arch/arm/mach-omap2/dma.c 	[IRQSTATUS_L1]	= { 0x000c, 0x00, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   43 arch/arm/mach-omap2/dma.c 	[IRQSTATUS_L2]	= { 0x0010, 0x00, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   44 arch/arm/mach-omap2/dma.c 	[IRQSTATUS_L3]	= { 0x0014, 0x00, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   45 arch/arm/mach-omap2/dma.c 	[IRQENABLE_L0]	= { 0x0018, 0x00, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   46 arch/arm/mach-omap2/dma.c 	[IRQENABLE_L1]	= { 0x001c, 0x00, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   47 arch/arm/mach-omap2/dma.c 	[IRQENABLE_L2]	= { 0x0020, 0x00, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   48 arch/arm/mach-omap2/dma.c 	[IRQENABLE_L3]	= { 0x0024, 0x00, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   49 arch/arm/mach-omap2/dma.c 	[SYSSTATUS]	= { 0x0028, 0x00, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   50 arch/arm/mach-omap2/dma.c 	[OCP_SYSCONFIG]	= { 0x002c, 0x00, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   51 arch/arm/mach-omap2/dma.c 	[CAPS_0]	= { 0x0064, 0x00, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   52 arch/arm/mach-omap2/dma.c 	[CAPS_2]	= { 0x006c, 0x00, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   53 arch/arm/mach-omap2/dma.c 	[CAPS_3]	= { 0x0070, 0x00, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   54 arch/arm/mach-omap2/dma.c 	[CAPS_4]	= { 0x0074, 0x00, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   57 arch/arm/mach-omap2/dma.c 	[CCR]		= { 0x0080, 0x60, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   58 arch/arm/mach-omap2/dma.c 	[CLNK_CTRL]	= { 0x0084, 0x60, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   59 arch/arm/mach-omap2/dma.c 	[CICR]		= { 0x0088, 0x60, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   60 arch/arm/mach-omap2/dma.c 	[CSR]		= { 0x008c, 0x60, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   61 arch/arm/mach-omap2/dma.c 	[CSDP]		= { 0x0090, 0x60, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   62 arch/arm/mach-omap2/dma.c 	[CEN]		= { 0x0094, 0x60, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   63 arch/arm/mach-omap2/dma.c 	[CFN]		= { 0x0098, 0x60, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   64 arch/arm/mach-omap2/dma.c 	[CSEI]		= { 0x00a4, 0x60, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   65 arch/arm/mach-omap2/dma.c 	[CSFI]		= { 0x00a8, 0x60, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   66 arch/arm/mach-omap2/dma.c 	[CDEI]		= { 0x00ac, 0x60, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   67 arch/arm/mach-omap2/dma.c 	[CDFI]		= { 0x00b0, 0x60, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   68 arch/arm/mach-omap2/dma.c 	[CSAC]		= { 0x00b4, 0x60, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   69 arch/arm/mach-omap2/dma.c 	[CDAC]		= { 0x00b8, 0x60, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   72 arch/arm/mach-omap2/dma.c 	[CSSA]		= { 0x009c, 0x60, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   73 arch/arm/mach-omap2/dma.c 	[CDSA]		= { 0x00a0, 0x60, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   74 arch/arm/mach-omap2/dma.c 	[CCEN]		= { 0x00bc, 0x60, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   75 arch/arm/mach-omap2/dma.c 	[CCFN]		= { 0x00c0, 0x60, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   76 arch/arm/mach-omap2/dma.c 	[COLOR]		= { 0x00c4, 0x60, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   79 arch/arm/mach-omap2/dma.c 	[CDP]		= { 0x00d0, 0x60, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   80 arch/arm/mach-omap2/dma.c 	[CNDP]		= { 0x00d4, 0x60, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT   81 arch/arm/mach-omap2/dma.c 	[CCDN]		= { 0x00d8, 0x60, OMAP_DMA_REG_32BIT },
OMAP_DMA_REG_32BIT  298 drivers/dma/ti/omap-dma.c 	case OMAP_DMA_REG_32BIT:
OMAP_DMA_REG_32BIT  318 drivers/dma/ti/omap-dma.c 	case OMAP_DMA_REG_32BIT: