OMAP44XX_CM1_REGADDR 49 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000) OMAP44XX_CM1_REGADDR 51 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040) OMAP44XX_CM1_REGADDR 55 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000) OMAP44XX_CM1_REGADDR 57 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008) OMAP44XX_CM1_REGADDR 59 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010) OMAP44XX_CM1_REGADDR 61 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020) OMAP44XX_CM1_REGADDR 63 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024) OMAP44XX_CM1_REGADDR 65 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028) OMAP44XX_CM1_REGADDR 67 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c) OMAP44XX_CM1_REGADDR 69 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030) OMAP44XX_CM1_REGADDR 71 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034) OMAP44XX_CM1_REGADDR 73 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038) OMAP44XX_CM1_REGADDR 75 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c) OMAP44XX_CM1_REGADDR 77 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0040) OMAP44XX_CM1_REGADDR 79 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044) OMAP44XX_CM1_REGADDR 81 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048) OMAP44XX_CM1_REGADDR 83 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c) OMAP44XX_CM1_REGADDR 85 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050) OMAP44XX_CM1_REGADDR 87 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0060) OMAP44XX_CM1_REGADDR 89 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0064) OMAP44XX_CM1_REGADDR 91 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0068) OMAP44XX_CM1_REGADDR 93 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x006c) OMAP44XX_CM1_REGADDR 95 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070) OMAP44XX_CM1_REGADDR 97 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088) OMAP44XX_CM1_REGADDR 99 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c) OMAP44XX_CM1_REGADDR 101 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c) OMAP44XX_CM1_REGADDR 103 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a0) OMAP44XX_CM1_REGADDR 105 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a4) OMAP44XX_CM1_REGADDR 107 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a8) OMAP44XX_CM1_REGADDR 109 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ac) OMAP44XX_CM1_REGADDR 111 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00b8) OMAP44XX_CM1_REGADDR 113 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc) OMAP44XX_CM1_REGADDR 115 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8) OMAP44XX_CM1_REGADDR 117 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc) OMAP44XX_CM1_REGADDR 119 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc) OMAP44XX_CM1_REGADDR 121 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e0) OMAP44XX_CM1_REGADDR 123 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e4) OMAP44XX_CM1_REGADDR 125 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e8) OMAP44XX_CM1_REGADDR 127 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec) OMAP44XX_CM1_REGADDR 129 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0) OMAP44XX_CM1_REGADDR 131 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4) OMAP44XX_CM1_REGADDR 133 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108) OMAP44XX_CM1_REGADDR 135 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c) OMAP44XX_CM1_REGADDR 137 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120) OMAP44XX_CM1_REGADDR 139 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0124) OMAP44XX_CM1_REGADDR 141 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0128) OMAP44XX_CM1_REGADDR 143 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x012c) OMAP44XX_CM1_REGADDR 145 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0130) OMAP44XX_CM1_REGADDR 147 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0138) OMAP44XX_CM1_REGADDR 149 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x013c) OMAP44XX_CM1_REGADDR 151 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140) OMAP44XX_CM1_REGADDR 153 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148) OMAP44XX_CM1_REGADDR 155 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c) OMAP44XX_CM1_REGADDR 157 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160) OMAP44XX_CM1_REGADDR 159 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0164) OMAP44XX_CM1_REGADDR 161 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0170) OMAP44XX_CM1_REGADDR 163 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0180) OMAP44XX_CM1_REGADDR 167 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0000) OMAP44XX_CM1_REGADDR 169 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0004) OMAP44XX_CM1_REGADDR 171 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0008) OMAP44XX_CM1_REGADDR 173 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0020) OMAP44XX_CM1_REGADDR 177 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0000) OMAP44XX_CM1_REGADDR 179 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0004) OMAP44XX_CM1_REGADDR 181 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0008) OMAP44XX_CM1_REGADDR 183 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0020) OMAP44XX_CM1_REGADDR 187 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0000) OMAP44XX_CM1_REGADDR 189 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0020) OMAP44XX_CM1_REGADDR 191 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0028) OMAP44XX_CM1_REGADDR 193 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0030) OMAP44XX_CM1_REGADDR 195 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0038) OMAP44XX_CM1_REGADDR 197 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0040) OMAP44XX_CM1_REGADDR 199 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0048) OMAP44XX_CM1_REGADDR 201 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0050) OMAP44XX_CM1_REGADDR 203 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0058) OMAP44XX_CM1_REGADDR 205 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0060) OMAP44XX_CM1_REGADDR 207 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0068) OMAP44XX_CM1_REGADDR 209 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0070) OMAP44XX_CM1_REGADDR 211 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0078) OMAP44XX_CM1_REGADDR 213 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0080) OMAP44XX_CM1_REGADDR 215 arch/arm/mach-omap2/cm1_44xx.h #define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)