OMAP4430_PRCM_MPU_CPU1_INST 284 arch/arm/mach-omap2/clockdomains44xx_data.c .cm_inst = OMAP4430_PRCM_MPU_CPU1_INST, OMAP4430_PRCM_MPU_CPU1_INST 168 arch/arm/mach-omap2/omap-mpuss-lowpower.c reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST, OMAP4430_PRCM_MPU_CPU1_INST 170 arch/arm/mach-omap2/omap-mpuss-lowpower.c omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST, OMAP4430_PRCM_MPU_CPU1_INST 170 arch/arm/mach-omap2/powerdomains44xx_data.c .prcm_offs = OMAP4430_PRCM_MPU_CPU1_INST, OMAP4430_PRCM_MPU_CPU1_INST 80 arch/arm/mach-omap2/prcm_mpu44xx.h #define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000) OMAP4430_PRCM_MPU_CPU1_INST 82 arch/arm/mach-omap2/prcm_mpu44xx.h #define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004) OMAP4430_PRCM_MPU_CPU1_INST 84 arch/arm/mach-omap2/prcm_mpu44xx.h #define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008) OMAP4430_PRCM_MPU_CPU1_INST 86 arch/arm/mach-omap2/prcm_mpu44xx.h #define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c) OMAP4430_PRCM_MPU_CPU1_INST 88 arch/arm/mach-omap2/prcm_mpu44xx.h #define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010) OMAP4430_PRCM_MPU_CPU1_INST 90 arch/arm/mach-omap2/prcm_mpu44xx.h #define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014) OMAP4430_PRCM_MPU_CPU1_INST 92 arch/arm/mach-omap2/prcm_mpu44xx.h #define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)