OMAP4430_PRCM_MPU_CPU0_INST  275 arch/arm/mach-omap2/clockdomains44xx_data.c 	.cm_inst	  = OMAP4430_PRCM_MPU_CPU0_INST,
OMAP4430_PRCM_MPU_CPU0_INST  173 arch/arm/mach-omap2/omap-mpuss-lowpower.c 		reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
OMAP4430_PRCM_MPU_CPU0_INST  175 arch/arm/mach-omap2/omap-mpuss-lowpower.c 		omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
OMAP4430_PRCM_MPU_CPU0_INST  153 arch/arm/mach-omap2/powerdomains44xx_data.c 	.prcm_offs	  = OMAP4430_PRCM_MPU_CPU0_INST,
OMAP4430_PRCM_MPU_CPU0_INST   64 arch/arm/mach-omap2/prcm_mpu44xx.h #define OMAP4430_PM_CPU0_PWRSTCTRL		OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
OMAP4430_PRCM_MPU_CPU0_INST   66 arch/arm/mach-omap2/prcm_mpu44xx.h #define OMAP4430_PM_CPU0_PWRSTST		OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
OMAP4430_PRCM_MPU_CPU0_INST   68 arch/arm/mach-omap2/prcm_mpu44xx.h #define OMAP4430_RM_CPU0_CPU0_CONTEXT		OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
OMAP4430_PRCM_MPU_CPU0_INST   70 arch/arm/mach-omap2/prcm_mpu44xx.h #define OMAP4430_RM_CPU0_CPU0_RSTCTRL		OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
OMAP4430_PRCM_MPU_CPU0_INST   72 arch/arm/mach-omap2/prcm_mpu44xx.h #define OMAP4430_RM_CPU0_CPU0_RSTST		OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
OMAP4430_PRCM_MPU_CPU0_INST   74 arch/arm/mach-omap2/prcm_mpu44xx.h #define OMAP4430_CM_CPU0_CPU0_CLKCTRL		OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
OMAP4430_PRCM_MPU_CPU0_INST   76 arch/arm/mach-omap2/prcm_mpu44xx.h #define OMAP4430_CM_CPU0_CLKSTCTRL		OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)