OMAP1_IO_ADDRESS 98 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), OMAP1_IO_ADDRESS 110 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1), OMAP1_IO_ADDRESS 132 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), OMAP1_IO_ADDRESS 151 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), OMAP1_IO_ADDRESS 162 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), OMAP1_IO_ADDRESS 175 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), OMAP1_IO_ADDRESS 188 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), OMAP1_IO_ADDRESS 212 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL), OMAP1_IO_ADDRESS 298 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), OMAP1_IO_ADDRESS 307 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), OMAP1_IO_ADDRESS 321 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), OMAP1_IO_ADDRESS 347 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), OMAP1_IO_ADDRESS 360 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), OMAP1_IO_ADDRESS 385 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), OMAP1_IO_ADDRESS 399 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), OMAP1_IO_ADDRESS 422 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), OMAP1_IO_ADDRESS 442 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), OMAP1_IO_ADDRESS 461 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), OMAP1_IO_ADDRESS 480 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), OMAP1_IO_ADDRESS 500 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), OMAP1_IO_ADDRESS 512 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL), OMAP1_IO_ADDRESS 522 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), OMAP1_IO_ADDRESS 533 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */ OMAP1_IO_ADDRESS 542 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), OMAP1_IO_ADDRESS 551 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), OMAP1_IO_ADDRESS 560 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), OMAP1_IO_ADDRESS 569 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), OMAP1_IO_ADDRESS 577 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL), OMAP1_IO_ADDRESS 595 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL), OMAP1_IO_ADDRESS 609 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), OMAP1_IO_ADDRESS 624 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), OMAP1_IO_ADDRESS 635 arch/arm/mach-omap1/clock_data.c .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), OMAP1_IO_ADDRESS 28 arch/arm/mach-omap1/include/mach/mtd-xip.h ((volatile xip_omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \ OMAP1_IO_ADDRESS 147 arch/arm/mach-omap1/io.c return __raw_readb(OMAP1_IO_ADDRESS(pa)); OMAP1_IO_ADDRESS 153 arch/arm/mach-omap1/io.c return __raw_readw(OMAP1_IO_ADDRESS(pa)); OMAP1_IO_ADDRESS 159 arch/arm/mach-omap1/io.c return __raw_readl(OMAP1_IO_ADDRESS(pa)); OMAP1_IO_ADDRESS 165 arch/arm/mach-omap1/io.c __raw_writeb(v, OMAP1_IO_ADDRESS(pa)); OMAP1_IO_ADDRESS 171 arch/arm/mach-omap1/io.c __raw_writew(v, OMAP1_IO_ADDRESS(pa)); OMAP1_IO_ADDRESS 177 arch/arm/mach-omap1/io.c __raw_writel(v, OMAP1_IO_ADDRESS(pa)); OMAP1_IO_ADDRESS 42 arch/arm/mach-omap1/pm.h #define CLKGEN_REG_ASM_BASE OMAP1_IO_ADDRESS(0xfffece00) OMAP1_IO_ADDRESS 46 arch/arm/mach-omap1/pm.h #define TCMIF_ASM_BASE OMAP1_IO_ADDRESS(0xfffecc00) OMAP1_IO_ADDRESS 52 arch/arm/mach-omap1/reset.c rs = __raw_readw(OMAP1_IO_ADDRESS(ARM_SYSST)); OMAP1_IO_ADDRESS 69 arch/arm/mach-omap1/time.c ((omap_mpu_timer_regs_t __iomem *)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \