OCTEON_IRQ_MBOX1 1513 arch/mips/cavium-octeon/octeon-irq.c 		OCTEON_IRQ_MBOX1, 0, 33, 0, chip_mbox, handle_percpu_irq);
OCTEON_IRQ_MBOX1 2093 arch/mips/cavium-octeon/octeon-irq.c 	irq_set_chip_and_handler(OCTEON_IRQ_MBOX1, &octeon_irq_chip_ciu2_mbox, handle_percpu_irq);