N_PHASES          166 drivers/gpu/drm/i915/display/intel_overlay.c 	u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
N_PHASES          167 drivers/gpu/drm/i915/display/intel_overlay.c 	u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
N_PHASES          168 drivers/gpu/drm/i915/display/intel_overlay.c 	u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
N_PHASES          169 drivers/gpu/drm/i915/display/intel_overlay.c 	u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
N_PHASES          170 drivers/gpu/drm/i915/display/intel_overlay.c 	u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
N_PHASES          171 drivers/gpu/drm/i915/display/intel_overlay.c 	u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
N_PHASES          172 drivers/gpu/drm/i915/display/intel_overlay.c 	u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
N_PHASES          173 drivers/gpu/drm/i915/display/intel_overlay.c 	u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
N_PHASES          553 drivers/gpu/drm/i915/display/intel_overlay.c static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = {
N_PHASES          573 drivers/gpu/drm/i915/display/intel_overlay.c static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = {