NV_VIO_SR_CLOCK_INDEX  221 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20);
NV_VIO_SR_CLOCK_INDEX  222 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1);
NV_VIO_SR_CLOCK_INDEX  330 drivers/gpu/drm/nouveau/dispnv04/crtc.c 		regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29;
NV_VIO_SR_CLOCK_INDEX  332 drivers/gpu/drm/nouveau/dispnv04/crtc.c 		regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21;
NV_VIO_SR_CLOCK_INDEX  156 drivers/gpu/drm/nouveau/dispnv04/dac.c 	saved_seq1 = NVReadVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX);
NV_VIO_SR_CLOCK_INDEX  157 drivers/gpu/drm/nouveau/dispnv04/dac.c 	NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1 & ~0x20);
NV_VIO_SR_CLOCK_INDEX  223 drivers/gpu/drm/nouveau/dispnv04/dac.c 	NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1);
NV_VIO_SR_CLOCK_INDEX  116 drivers/gpu/drm/nouveau/dispnv04/hw.c 	seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX);
NV_VIO_SR_CLOCK_INDEX  120 drivers/gpu/drm/nouveau/dispnv04/hw.c 		NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);
NV_VIO_SR_CLOCK_INDEX  122 drivers/gpu/drm/nouveau/dispnv04/hw.c 		NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20);
NV_VIO_SR_CLOCK_INDEX  245 drivers/gpu/drm/nouveau/dispnv04/hw.h 	uint8_t seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX);
NV_VIO_SR_CLOCK_INDEX  249 drivers/gpu/drm/nouveau/dispnv04/hw.h 		NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);
NV_VIO_SR_CLOCK_INDEX  252 drivers/gpu/drm/nouveau/dispnv04/hw.h 		NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20);   /* reenable display */