NV_CIO_CRE_RPC1_INDEX  191 drivers/gpu/drm/nouveau/dispnv04/crtc.c 					NV_CIO_CRE_RPC1_INDEX) & ~0xC0;
NV_CIO_CRE_RPC1_INDEX  228 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A);
NV_CIO_CRE_RPC1_INDEX  387 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ?
NV_CIO_CRE_RPC1_INDEX  168 drivers/gpu/drm/nouveau/dispnv04/dac.c 	saved_rpc1 = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX);
NV_CIO_CRE_RPC1_INDEX  169 drivers/gpu/drm/nouveau/dispnv04/dac.c 	NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1 & ~0xc0);
NV_CIO_CRE_RPC1_INDEX  222 drivers/gpu/drm/nouveau/dispnv04/dac.c 	NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1);
NV_CIO_CRE_RPC1_INDEX  284 drivers/gpu/drm/nouveau/dispnv04/dac.c 	if (!(NVReadVgaCrtc(dev, head, NV_CIO_CRE_RPC1_INDEX) & 0xC0))
NV_CIO_CRE_RPC1_INDEX  597 drivers/gpu/drm/nouveau/dispnv04/hw.c 	rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
NV_CIO_CRE_RPC1_INDEX  711 drivers/gpu/drm/nouveau/dispnv04/hw.c 	wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
NV_CIO_CRE_RPC1_INDEX   89 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c 		crtc1A = NVReadVgaCrtc(dev, head, NV_CIO_CRE_RPC1_INDEX);
NV_CIO_CRE_RPC1_INDEX   97 drivers/gpu/drm/nouveau/dispnv04/tvnv04.c 		NVWriteVgaCrtc(dev, head, NV_CIO_CRE_RPC1_INDEX, crtc1A);