NVWriteVgaSeq     222 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1);
NVWriteVgaSeq     157 drivers/gpu/drm/nouveau/dispnv04/dac.c 	NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1 & ~0x20);
NVWriteVgaSeq     223 drivers/gpu/drm/nouveau/dispnv04/dac.c 	NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1);
NVWriteVgaSeq     120 drivers/gpu/drm/nouveau/dispnv04/hw.c 		NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);
NVWriteVgaSeq     122 drivers/gpu/drm/nouveau/dispnv04/hw.c 		NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20);
NVWriteVgaSeq     294 drivers/gpu/drm/nouveau/dispnv04/hw.c 	NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, 1 << plane);
NVWriteVgaSeq     349 drivers/gpu/drm/nouveau/dispnv04/hw.c 	NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, 0x6);
NVWriteVgaSeq     362 drivers/gpu/drm/nouveau/dispnv04/hw.c 	NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, seq2);
NVWriteVgaSeq     363 drivers/gpu/drm/nouveau/dispnv04/hw.c 	NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, seq4);
NVWriteVgaSeq     571 drivers/gpu/drm/nouveau/dispnv04/hw.c 		NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]);
NVWriteVgaSeq      37 drivers/gpu/drm/nouveau/dispnv04/hw.h void NVWriteVgaSeq(struct drm_device *, int head, uint8_t index, uint8_t value);
NVWriteVgaSeq     240 drivers/gpu/drm/nouveau/dispnv04/hw.h 	NVWriteVgaSeq(dev, head, NV_VIO_SR_RESET_INDEX, start ? 0x1 : 0x3);
NVWriteVgaSeq     249 drivers/gpu/drm/nouveau/dispnv04/hw.h 		NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);
NVWriteVgaSeq     252 drivers/gpu/drm/nouveau/dispnv04/hw.h 		NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20);   /* reenable display */